Method for programming a threedimensional memory array incorporating serial chain diode stack
First Claim
1. In a multi-level memory array comprising a plurality of conductors on each level of the memory array, forming a memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality in common with cells of at least one adjacent level, a method of writing a selected memory cell comprising the steps of:
- biasing a first conductor coupled to an anode terminal of the selected memory cell to a first voltage;
biasing a second conductor coupled to a cathode terminal of the selected memory cell to a second voltage lower than the first voltage;
biasing at least one of a group of unselected conductors on the same level as the first conductor to a third voltage between the first and second voltages and at an offset from the second voltage; and
biasing at least one of a group of unselected conductors on the same level as the second conductor to a fourth voltage between the first and second voltages and at an offset from the first voltage.
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Abstract
A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
78 Citations
6 Claims
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1. In a multi-level memory array comprising a plurality of conductors on each level of the memory array, forming a memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality in common with cells of at least one adjacent level, a method of writing a selected memory cell comprising the steps of:
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biasing a first conductor coupled to an anode terminal of the selected memory cell to a first voltage;
biasing a second conductor coupled to a cathode terminal of the selected memory cell to a second voltage lower than the first voltage;
biasing at least one of a group of unselected conductors on the same level as the first conductor to a third voltage between the first and second voltages and at an offset from the second voltage; and
biasing at least one of a group of unselected conductors on the same level as the second conductor to a fourth voltage between the first and second voltages and at an offset from the first voltage. - View Dependent Claims (2, 3)
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4. In a multi-level memory array comprising a plurality of conductors on each level of the memory array, forming a memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality in common with cells of at least one adjacent level, a method for programming a selected memory cell within a selected memory plane, said method comprising the steps of:
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forward biasing the selected memory cell with a programming voltage;
reverse biasing memory cells within the selected memory plane that do not share a conductor with the selected memory cell; and
forward biasing unselected memory cells on at least memory planes adjacent to the selected memory plane, but only those cells that do not share a conductor with the selected memory cell, to a voltage between zero and a turn-on voltage for the memory cell. - View Dependent Claims (5, 6)
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Specification