Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability

• US 20030027396A1
• Filed: 07/31/2001
• Published: 02/06/2003
• Est. Priority Date: 07/31/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Yamamoto, Taku, Yamazaki, Katsuya, Stefanov, Evgueniy N., Tanaka, Masami, Hossain, Zia, Imam, Mohamed, Fulton, Joe, Enosawa, Yoshio
• Granted Patent: US 6,773,997 B2
• Time in Patent Office: Days
• US Class Current: 438/306
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Claims

1. A method of manufacturing a semiconductor device comprising:

providing a substrate of a first conductivity type;

forming a first region of a second conductivity type within the substrate to provide an extended drain region;

disposing a first island of field oxide at a top of the substrate within the first region;

implanting a second region of a first conductivity type in the first region, adjacent to the first island of field oxide to balance charges in the first region;

implanting a source diffusion region and a drain diffusion region in the semiconductor device; and

annealing the semiconductor device to diffuse the second region, the source diffusion region and the drain diffusion region.

2. The method of claim 1 further comprising:

applying an insulating layer over the semiconductor device, the insulating layer having a thickness less than the first island of field oxide; and

implanting the second region of the second conductivity type through the insulating layer.

3. The method of claim 1, wherein the step of forming a first region further comprises:

forming a first area of first dopant concentration by performing a first area implant; and

forming a second area of second dopant concentration different than the first dopant concentration by performing a second area implant, the second area implant is laterally offset from the first area.

4. The method of claim 1 further comprising:

forming a second island of field oxide at the top surface of the substrate, within the first region, and laterally separated from the first island of field oxide.

5. The method of claim 4, further comprising forming a gate region overlying the first island of field oxide.

6. The method of claim 4, further comprising forming a conductive region overlying the second island of field oxide.

7. The method of claim 1, further comprising implanting additional regions of the first conductivity type into the first region.

8. The method of claim 1, further comprising forming a diffused region of the first conductivity type.

9. The method of claim 8, further comprising forming a source diffusion region in the diffused region of the first conductivity type.

10. The method of claim 1, further comprising forming a drain diffusion region at the surface of the first region.

11. A method of manufacturing a semiconductor device comprising:

providing a substrate of a first conductivity type;

forming a first region of a second conductivity type within the substrate;

disposing a first island of dielectric material at a top of the substrate within the first region;

implanting a second region of a first conductivity type in the first region adjacent to the first island of dielectric material; and

disposing an insulating layer over the second region having a thickness less than the first island of dielectric material.

12. The method of claim 11, wherein the step of forming a first region further comprises:

forming a first area of first dopant concentration by performing a first area implant; and

forming a second area of second dopant concentration different than the first dopant concentration by performing a second area implant, the second area implant is laterally offset from the first area.

13. The method of claim 11 further comprising:

forming a second island of dielectric material at the top surface of the substrate, within the first region and laterally separated from the first island of dielectric material.

14. The method of claim 11, further comprising implanting additional regions of the first conductivity type into the first region.

15. A method of manufacturing a semiconductor device comprising:

providing a substrate of a first conductivity type;

forming a first region of a second conductivity type within the substrate;

disposing a first island of dielectric material at a top of the substrate within the first region; and

disposing a second island of dielectric material at a top of the substrate within the first region laterally separated from the first island of dielectric material; and

implanting a second region of a first conductivity type in the first region between the first and second islands of dielectric material.

16. The method of claim 15, further comprising forming a conductive gate region overlying the first island of field oxide.

17. The method of claim 16, further comprising forming a conductive region overlying the second island of field oxide.

18. The method of claim 15, wherein the step of forming a first region further comprises:

forming a first area of first dopant concentration by performing a first area implant; and

forming a second area of second dopant concentration different than the first dopant concentration by performing a second area implant, the second area implant is laterally offset from the first area.

19. The method of claim 16, further comprising implanting additional regions of the first conductivity type into the first region.

20. The method of claim 15 further comprising:

applying an insulating layer over the semiconductor device, the insulating layer having a thickness less than the first island of dielectric material; and

implanting the second region of the second conductivity type through the insulating layer.