ASF memory loading and handling system and method

• US 20030028633A1
• Filed: 04/24/2002
• Published: 02/06/2003
• Est. Priority Date: 04/24/2001
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Naylor, Andrew M., Lindsay, Steven B., Hwang, Andrew S.
• Granted Patent: US 7,451,335 B2
• Time in Patent Office: Days
• US Class Current: 709/224
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/06 Management of faults, events, alarms or notifications
• CPC Class Codes: H04L 41/08 Configuration management of networks or network elements address allocation H04L61/50
• CPC Class Codes: H04L 41/0803 Configuration setting
• CPC Class Codes: H04L 41/082 the condition being updates or upgrades of network functionality
• CPC Class Codes: H04L 41/0856 by backing up or archiving configuration information
• CPC Class Codes: H04L 41/0869 Validating the configuration within one network element
• CPC Class Codes: H04L 41/147 for predicting network behaviour
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/40 for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Techniques are disclosed for providing system manageability for computing systems operating under OS-absent conditions. In particular, techniques are disclosed for providing fully functional system management capabilities even when the primary power source for the computing system is disabled. One aspect of the invention provides an ASF-compliant device that selectively supports partial ASF functionality. One aspect of the invention provides an ASF-compliant device that runs ASF firmware that is stored in nonvolatile memory and can be upgraded in the field. One aspect of the invention provides an ASF-compliant device that runs ASF firmware and that can load portions of the ASF firmware into its memory in stages.

Claims

1. An alert sending device comprising:

at least one processor for performing alert standard format operations, wherein the processor selectively executes a portion of the alert standard format operations based on at least one criteria.

2. The alert sending device of claim 1 wherein the at least one processor only calls subroutines associated with enabled alert standard format operations.

3. The alert sending device of claim 1 further comprising at least one sensor for providing a signal to the at least one processor, the signal indicative of whether the alert sensing device is powered by an auxiliary power source, wherein the criteria is whether the alert sending device is operating on auxiliary power.

4. The alert sending device of claim 1 wherein the processor uses at least one configuration flag to determine which portion of the alert standard format operations are executed.

5. The alert sending device of claim 1 wherein the alert standard format operations include watchdog alerts and the processor does not perform watchdog alert operations when the alert sending device is operating on auxiliary power.

6. The alert sending device of claim 1 wherein the at least one processor is incorporated in a network controller integrated circuit.

7. The alert sending device of claim 1 wherein the at least one processor is incorporated in a network interface card.

8. A method of performing alert standard format operations comprising the steps of:

retrieving at least one criteria associated with alert standard format operations to be performed by an alert sending device;

identifying enabled portions of the alert standard format operations according to the at least one criteria; and

executing code associated with the enabled portions of the alert standard format operations.

9. The method of claim 8 further comprising the step of generating a signal indicative of whether the alert sensing device is powered by an auxiliary power source, wherein the criteria is whether the alert sending device is operating on auxiliary power.

10. The method of claim 8 further comprising the step of using configuration information to identify the enables portions of the alert standard format operations.

11. The method of claim 10 wherein the configuration information is stored in a nonvolatile data memory.

12. The method of claim 8 wherein the alert standard format operations include watchdog alerts and watchdog alert operations are not performed when an alert sending device is operating on auxiliary power.

13. A network controller comprising:

at least one data memory for storing alert standard format code associated with a plurality of alert standard format operations; and

at least one processor for selectively executing a portion of the alert standard format operations based on at least one criteria.

14. The network controller of claim 13 further comprising at least one sensor for providing a signal to the at least one processor, the signal indicative of whether the alert sensing device is powered by an auxiliary power source, wherein the criteria is whether the network controller is operating on auxiliary power.

15. The network controller of claim 13 wherein the processor uses at least one configuration flag to determine which portion of the alert standard format operations are executed.

16. The network controller of claim 13 wherein the alert standard format operations include watchdog alerts and the processor does not perform watchdog alert operations when the network controller is operating on auxiliary power.

17. A network controller, connected to be powered by at least one PCI bus primary power source or a PCI bus auxiliary power source, for performing alert standard format operations when the alert sensing device is powered by the auxiliary power source, the network controller comprising:

at least one data memory, powered by the auxiliary power source, for storing alert standard format code associated with a plurality of alert standard format operations and for storing configuration information; and

at least one processor, powered by the auxiliary power source and coupled to the at least one sensor, for selectively executing a portion of the alert standard format operations according to the configuration information.

18. The network controller of claim 17 wherein the configuration information is indicative of disabled alert standard format operations.

19. An alert sending device comprising:

at least one field upgradeable nonvolatile data memory for storing alert standard format code; and

at least one processor for executing the alert standard format code.

20. The alert sending device of claim 19 wherein the at least one nonvolatile data memory comprises a SEEPROM.

21. The alert sending device of claim 19 wherein the at least one nonvolatile data memory comprises a flash memory.

22. The alert sending device of claim 19 further comprising means for modifying the alert standard format code stored in the at least one nonvolatile data memory.

23. The alert sending device of claim 19 further comprising a bus interface for modifying the alert standard format code stored in the at least one nonvolatile data memory.

24. A method of updating alert standard format code for an alert sending device comprising the steps of:

storing alert standard format code in at least one field upgradeable nonvolatile data memory; and

modifying the alert standard format code in at least one field upgradeable nonvolatile data memory in the field.

25. The method of claim 24 wherein the at least one nonvolatile data memory comprises a SEEPROM.

26. The method of claim 24 wherein the at least one nonvolatile data memory comprises a flash memory.

27. The method of claim 24 further comprising the step of modifying the alert standard format code stored in the at least one nonvolatile data memory.

28. The method of claim 24 further comprising the step of modifying the alert standard format code stored in the at least one nonvolatile data memory via a bus interface.

29. A network controller comprising:

at least one nonvolatile data memory for storing alert standard format code; and

at least one processor for executing the alert standard format code.

30. The network controller of claim 29 wherein the at least one nonvolatile data memory comprises a SEEPROM.

31. The network controller of claim 29 wherein the at least one nonvolatile data memory comprises a flash memory.

32. The network controller of claim 29 further comprising means for modifying the alert standard format code stored in the at least one nonvolatile data memory.

33. The network controller of claim 29 further comprising a bus interface for modifying the alert standard format code stored in the at least one nonvolatile data memory.

34. The network controller of claim 29 wherein the at least one processor is incorporated in a network controller integrated circuit.

35. The network controller of claim 29 comprising at least one network interface card.

36. An alert sending device comprising:

at least one data memory for storing alert standard format code associated with a plurality of operations;

at least one data memory for storing code for execution; and

at least one processor for sequentially loading alert standard format code associated with each of the operations from the at least one data memory for storing alert standard format code to the at least one data memory for storing code for execution.

37. The alert sending device of claim 36 wherein the at least one processor loads a first set of code associated with a first one of the operations, then executes the first set of code, then loads a second set of code associated with a second one of the operations, then executes the second set of code.

38. The alert sending device of claim 36 wherein the at least one processor loads the first set of code at a first set of memory locations and the second set of code at a second set of memory locations, wherein at least a portion of the second set of memory locations overlaps at least a portion of the first set of memory locations.

39. A method of loading code associated with alert format standard operations for an alert sending device comprising the steps of:

storing alert standard format code associated with a plurality of operations in at least one data memory; and

loading alert standard format code associated with each of the operations from at least one data memory for storing alert standard format code to at least one data memory for storing code for execution.

40. The method of claim 39 further comprising the steps of:

loading a first set of code associated with a first one of the operations;

executing the first set of code;

loading a second set of code associated with a second one of the operations; and

executing the second set of code.

41. The method of claim 40 further comprising the steps of:

loading the first set of code at a first set of memory locations; and

loading the second set of code at a second set of memory locations, wherein the at least a portion of the second set of memory locations overlaps at least a portion of the first set of memory locations.