Low overhead interrupt
First Claim
1. A method for processing a low-overhead interrupt, comprising:
- detecting the occurrence of an interrupt condition that requires servicing;
determining that the interrupt condition corresponds to a fast interrupt;
loading a first instruction of an interrupt service routine (ISR) into an instruction register for immediate execution;
loading an address of a second instruction within the ISR into a program counter; and
fetching the second ISR instruction while executing the first ISR instruction.
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Accused Products
Abstract
A method and processor for interrupt processing operate to save processor cycles during the handling of interrupts. More particularly, upon an interrupt, the first instruction from an interrupt service routine (ISR) is loaded into an instruction register for immediate execution to save at least one cycle of interrupt instruction fetching. Simultaneously, the address of the second instruction from the ISR is stored into a program counter. Also, the next instruction in the regular program cycle for execution is taken from a prefetch register and stored in a holding register (or to the stack). Subsequently, the second instruction from the ISR is fetched and executed and the interrupt is serviced. When finished, the next regular instruction for execution is loaded into the prefetch register from the holding register (or stack) for subsequent execution. The program counter and a status register are restored from the stack. In the next cycle, the instruction from the holding register is executed and the following instruction is fetched into the prefetch. These steps save at least one cycle in processing interrupts.
109 Citations
15 Claims
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1. A method for processing a low-overhead interrupt, comprising:
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detecting the occurrence of an interrupt condition that requires servicing;
determining that the interrupt condition corresponds to a fast interrupt;
loading a first instruction of an interrupt service routine (ISR) into an instruction register for immediate execution;
loading an address of a second instruction within the ISR into a program counter; and
fetching the second ISR instruction while executing the first ISR instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A processor for handling low-overhead interrupts, comprising:
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a first interrupt instruction register storing the first interrupt instruction of a plurality of interrupt service routines;
a holding register;
an interrupt vector register;
a program counter; and
interrupt logic coupled to the registers, upon an interrupt, the interrupt logic a) loading a first instruction of an interrupt service routine (ISR) from the first interrupt instruction register into an instruction register for immediate execution and b) loading an address of a second instruction within the ISR into the program counter based on the interrupt vector register and executing the ISR. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification