Memory apparatus

• US 20030028733A1
• Filed: 06/13/2002
• Published: 02/06/2003
• Est. Priority Date: 06/13/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Maruyama, Junichi, Iguchi, Shinya, Nakamura, Kazuo, Tsunoda, Motoyasu
• Granted Patent: US 7,062,618 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

A memory apparatus having a volatile memory for storing data from a host, a nonvolatile memory capable of storing the data stored in the volatile memory, and electrically deleting the data, and a control circuit for controlling data transfer between the volatile memory and the nonvolatile memory. A capacity of a data storage area of the volatile memory is larger than that of a data storage area of the nonvolatile memory.

Claims

1. A memory apparatus comprising:

a volatile memory for storing data from a host;

a nonvolatile memory capable of storing the data stored in the volatile memory, and electrically deleting the data; and

a control circuit for controlling data transfer between the volatile memory and the nonvolatile memory,

wherein a capacity of a data storage area of the volatile memory is larger than that of a data storage area of the nonvolatile memory.

2. The memory apparatus according to claim 1, wherein the control circuit transfers the data stored in the volatile memory to the volatile memory when power supply from the host is started, and transfers the data stored in the volatile memory to the nonvolatile memory when the power supply from the host is stopped.

3. The memory apparatus according to claim 1, further comprising a control register for storing control information used by the control circuit,

wherein the nonvolatile memory includes a control register storage area for storing the control information set in the control register.

4. The memory apparatus according to claim 1, further comprising address correspondence information for setting correspondence between an address of the volatile memory and an address of the nonvolatile memory,

wherein the control circuit changes the correspondence between the address of the volatile memory and the address of the nonvolatile memory in the address correspondence information.

5. The memory apparatus according to claim 4, wherein the control circuit changes the correspondence between the address of the volatile memory and the address of the nonvolatile memory in the address correspondence information according to the number of times of deleting the data in the nonvolatile memory or failure of the data storage area.

11. The memory apparatus according to claim 5, wherein the interface includes an interface according to a standard of a memory card.

6. A memory apparatus comprising:

a volatile memory;

a nonvolatile memory; and

a control circuit for controlling data transfer between the volatile memory and the nonvolatile memory,

wherein the control circuit receives a command from a host, interprets the command, and starts the data transfer according to the interpreted command.

7. A memory apparatus comprising:

a volatile memory;

a nonvolatile memory; and

a control circuit for controlling data transfer between the volatile memory and the nonvolatile memory,

wherein the control circuit starts the data transfer according to an access command to a predetermined address on the volatile memory from a host.

8. A memory apparatus comprising:

a volatile memory;

a nonvolatile memory;

a control circuit for controlling data reading/writing in the volatile memory and the nonvolatile memory;

a first interface positioned between the host and the control circuit to input/output data read/written in the volatile memory; and

a second interface positioned between the host and the control circuit to input/output data read/written in the nonvolatile memory.

9. The memory apparatus according to claim 8, wherein the control circuit starts data transfer between the volatile memory and the nonvolatile memory according to a command inputted through the second interface.

10. A memory apparatus comprising:

a volatile memory;

a nonvolatile memory;

a control circuit for controlling data reading/writing in the volatile memory and the nonvolatile memory; and

an interface positioned between a host and the control circuit to input/output data read/written in the volatile memory,

wherein the interface inputs/outputs data read/written in the nonvolatile memory.

12. A memory apparatus comprising:

a volatile memory;

a flash memory;

a control circuit for controlling data transfer between the volatile memory and the flash memory; and

a holding circuit for holding data transferred between a DRAM and the flash memory.

13. A memory apparatus comprising:

a recording unit including a failed area, capable of accessing information by a predetermined unit;

a recording unit control circuit for controlling the recording unit;

a buffer memory for temporarily recording data transmitted/received with the recording unit;

a volatile memory for saving information for managing the failed area in the recording unit;

a failure management circuit for processing information of the volatile memory;

an interface control circuit having means for processing accessing from a host and issuing operation instructions to the recording unit control circuit and the failure management circuit;

means for dividing the recording unit into a plurality of areas, and individually managing the areas;

means for securing and managing an alternative area for replacing a failed area included in the area by each divided unit, and an area likely to fail; and

means for changing an access destination to access the alternative area instead when the host accesses the failed area.

14. The memory apparatus according to claim 13, further comprising means for executing sequential substitution processing by circuits according to failure characteristics, the recording unit having plural kinds of failure characteristics.

15. The memory apparatus according to claim 14, wherein the failure management circuit includes a programmable sequencer, and a ROM for recording a sequence, and a sequence code can be changed by replacing the ROM.

16. The memory apparatus according to claim 14, wherein the failure management circuit includes a programmable sequencer, and a RAM for holding a sequence, a sequence code is read from the recording unit, and saved in the sequence RAM at the time of starting, and the sequence code can be changed by executing the sequence code at the sequencer.