Method and system for digital signal processing in an adaptive computing engine
First Claim
1. A system for digital signal processing within an adaptive computing engine, the system comprising:
- a mini-matrix, the mini-matrix comprising a set of composite blocks, each composite block capable of executing a predetermined set of instructions;
a sequencer for controlling the set of composite blocks and directing instructions among the set of composite blocks based on a dataflow graph;
a data network for transmitting data to and from the set of composite blocks and to the sequencer; and
a status network for routing status word data resulting from instruction execution in the set of composite blocks.
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Abstract
Aspects of a method and system for digital signal processing within an adaptive computing engine are described. These aspects include a mini-matrix, the mini-matrix comprising a set of composite blocks, each composite block capable of executing a predetermined set of instructions. A sequencer is included for controlling the set of composite blocks and directing instructions among the set of composite blocks based on a data-flow graph. Further, a data network is included and transmits data to and from the set of composite blocks and to the sequencer, while a status network routes status word data resulting from instruction execution in the set of composite blocks. With the present invention, an effective combination of hardware resources is provided in a manner that provides multi-bit digital signal processing capabilities for an embedded system environment, particularly in an implementation of an adaptive computing engine. These and other advantages will become readily apparent from the following detailed description and accompanying drawings.
59 Citations
24 Claims
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1. A system for digital signal processing within an adaptive computing engine, the system comprising:
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a mini-matrix, the mini-matrix comprising a set of composite blocks, each composite block capable of executing a predetermined set of instructions;
a sequencer for controlling the set of composite blocks and directing instructions among the set of composite blocks based on a dataflow graph;
a data network for transmitting data to and from the set of composite blocks and to the sequencer; and
a status network for routing status word data resulting from instruction execution in the set of composite blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for digital signal processing within an adaptive computing engine, the system comprising:
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designating a set of composite blocks as a mini-matrix, each composite block capable of executing a predetermined set of instructions;
utilizing a sequencer for controlling the set of composite blocks and directing instructions among the set of composite blocks based on a dataflow graph;
providing a data network for transmitting data to and from the set of composite blocks and to the sequencer; and
providing a status network for routing status word data resulting from instruction execution in the set of composite blocks. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A system for digital signal processing in an adaptive computing engine, the system comprising:
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a set of four computation blocks designated as a mini-matrix, each of the four computation blocks comprising;
first and second register files for storing operand data;
a multiplier-ALU-shifter coupled to the first and second register files for performing an instruction and outputting results data; and
an accumulator register file coupled to the multiplier-ALU-shifter for storing accumulation data; and
a sequencer for controlling the set of four composite blocks and directing instructions among the set of four composite blocks based on a dataflow graph. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification