Shared memory control between detector framing node and processor

• US 20030030004A1
• Filed: 01/31/2001
• Published: 02/13/2003
• Est. Priority Date: 01/31/2001
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Van Stralen, Nick Andrew, Nieters, Edward James, Dixon, Walter Vincent
• Granted Patent: US 6,753,873 B2
• Time in Patent Office: Days
• US Class Current: 250/370.09
• CPC Class Codes: A61B 6/541 involving acquisition triggered by a physiological signal
• CPC Class Codes: A61B 6/56 Details of data transmission or power supply, e.g. use of slip rings
• CPC Class Codes: G01N 2223/419 computed tomograph
• CPC Class Codes: G01N 2223/612 biological material
• CPC Class Codes: G01N 23/046 using tomography, e.g. computed tomography [CT]
• CPC Class Codes: H04N 23/30 for generating image signals from X-rays
• CPC Class Codes: H04N 5/32 Transforming X-rays cameras or camera modules for generating image signals from X-rays H04N23/30; circuitry of SSIS for transforming X-rays into image signals H04N25/30

Abstract

An imaging system shares control of host memory between a detector framing node and a host processor. The detector framing node is programmable to control generation and reception of image data. Image data is acquired and communicated to host memory independently from control by a host operating system. The detector framing node controls events according to an event instruction sequence and communicates received image data to the host memory through a computer communication bus. Image data is received by the detector framing node from a flat panel detector. Host memory has a first section managed by the host operating system and a second section not managed by the host operating system. Image data is communicated from the detector framing node into the second section of host memory.

Claims

1. An image data control system, comprising:

at least one host processor executing operations with a host operating system;

a host memory having a first section managed by the host operating system for storing the host operating system and executable program code, and a second section not managed by the host operating system for storing image data;

a computer communication bus connecting said at least one host processor to said host memory and defining a protocol for communication along said computer communication bus; and

a detector framing node communicating with said at least one host processor by way of said computer communication bus, said detector framing node receiving image data from an image detection system and controlling communication of the image data to the host memory over said computer communication bus.

2. The system according to claim 1, wherein the first section of said host memory and the second section of said host memory are addressed along said computer communication bus, said detector framing node comprising:

a plurality of frame buffer memory units, each having unique memory addresses that are addressed along said computer communication bus such that said detector framing node controls transfer of the image data from the frame buffer memory units to said host memory.

3. The system according to claim 1, wherein said detector framing node copies the image data from the plurality of frame buffer memory units into the second section of host memory continuously without management from the host operating system.

4. The system according to claim 1, wherein said detector framing node copies the image data to the second section with respect to an assignable host memory base address.

5. The system according to claim 1, wherein said computer communication bus is a PCI bus and said detector framing node receives the image data independently from communication with the host memory such that said detector framing node continues to receive the image data during data transfer interruption along the PCI bus.

6. The system according to claim 5, wherein said detector framing node receives and stores the image data into the frame buffer memory units in real time.

7. The system according to claim 5, wherein said detector framing node communicates with said host memory over the PCI bus in parallel while said detector framing node receives the image data from an image detection system.

8. The system according to claim 7, wherein said detector framing node receives the image data from the image detection system serially.

9. The system according to claim 6, wherein the received image data is radioscopic image data, the image detection system is an x-ray image detection system, and the serial data is communicated from the x-ray image detection system to the detector framing node over an image detection bus.

10. The system according to claim 9, wherein the image detection bus is an optical fiber data link.

11. The system according to claim 1, wherein said detector framing node selectably receives image data from a cardiac/surgical digital x-ray panel outputting at least 1024 columns×

1024 rows of data;

a radiography digital x-ray panel outputting at least 2048 columns×

2048 rows of data;

or a mammography digital x-ray panel outputting at least 1920 columns×

2304 rows of data.

12. The system according to claim 1, wherein said detector framing node selectably receives the image data from a flat panel detector outputting a predetermined number of columns and a predetermined number of rows of the image data.

13. The system according to claim 1, wherein said detector framing node selectably receives the image data from a flat panel detector outputting an arbitrary number of columns and an arbitrary number of rows of the image data.

14. The system according to claim 1, wherein said detector framing node receives the image data from a single panel x-ray detection panel, such that rows of image data are sequentially read out and transferred to said detector framing node, or a split panel x-ray detection panel, such that pairs of rows of image data are simultaneously read out before transfer to said detector framing node.

15. The system according to claim 1, wherein said detector framing node receives a plurality of event instructions from said at least one host processor through said computer communication bus for controlling a radiation generation system, the plurality of event instructions forming an event sequence, which is stored in the first section of said host memory and communicated into an event queue of said detector framing node for execution in real time at predetermined timing intervals.

16. The system according to claim 15, wherein the event sequence is communicated to the event queue by way of an acquisition control unit in said detector framing node, wherein the event sequence controls initiation, timing, and stopping of the generation of radiation by the radiation generation system.

17. The system according to claim 1, wherein said detector framing node receives a plurality of event instructions from said at least one host processor through said computer communication bus for controlling said detector framing node, the plurality of event instructions forming an event sequence, which is stored in the first section of said host memory and communicated into an event queue of said detector framing node for execution in real time at predetermined timing intervals.

18. The system according to claim 1, wherein the image data is communicated from said detector framing node to the second section of host memory in groups of 512 continuous data cycles of 32 bit words starting at a single designed base address.

19. The system according to claim 1, wherein said detector framing node receives the image data from the image detection system in real time.

20. The system according to claim 1, wherein the image data is radioscopic image data.

21. The system according to claim 1, wherein the operating system is a non-real time operating system.

22. The system according to claim 21, wherein the operating system is a task based operating system.

23. The system according to claim 1, wherein the operating system is a task based operating system.

24. The system according to claim 1, wherein the operating system is a real time operating system.

25. The system according to claim 1, wherein a host application running on said host processor prepares a list of physical addresses for storing the image data in said host memory, and the host application transfers the list of physical addresses to registers in said detector framing node such that said detector framing node transfers the image data to locations specified by the physical address without management by the host operating system.

26. The system according to claim 1, wherein the second portion of said host memory is divided into a plurality of buffers with the physical address of each buffer aligned on a host memory page boundary.

27. The system according to claim 26, wherein each buffer is physically contiguous such that said detector framing node does not perform scatter-gather direct memory access during communication of the image data.

28. An image data control system, comprising:

a host computer comprising;

at least one host processor executing operations with a host operating system,

a host memory having a first section managed by a host operating system for storing the host operating system and executable program code under control of the host operating system, and having a second section not managed by the host operating system for storing image data, and

a computer communication bus connecting the at least one host processor and the host memory, and defining a protocol for communication;

a detector framing node receiving instructions from the host processor and transferring the image data to the second section of the host memory by way of the computer communication bus;

a radiation generation system responding to instructions from said detector framing node to generate radiation; and

an image detection system responding to instructions from said detector framing node to detect the radiation, convert the detected radiation into the image data, and communicate the image data to said detector framing node.

29. The image system according to claim 28, said detector framing node further comprising:

a detector framing node memory unit to receive the image data from the image detection system, and

a computer communication interface to transfer the image data from the detector framing node memory unit according to the protocol defined by the computer communication bus without memory management by the host operating system.

30. The image system according to claim 28, wherein the image data is transferred from said detector framing node memory unit without management by the host operating system.

31. The image system according to claim 28, wherein the image data is formed as an image frame and the image frame is transferred from said detector framing node memory unit to the second section of the host memory continuously such that the image frame is stored in continuous, sequential memory sections of the host memory.

32. The image system according to claim 28, wherein the computer communication bus is a PCI bus, and said detector framing node receives the image data independently from communication with the at least one host processor such that the detector framing node continues to receive the image data from the image detection system during interruption of the PCI bus.

33. The image system according to claim 32, said detector framing node communicating with the at least one host processor over the PCI bus in parallel while said detector framing node receives the image data from the image detection system in serial.

34. The image system according to claim 28, wherein the image data is radioscopic image data, the image detection system is an x-ray image detection system, and the serial data is communicated from the x-ray image detection system to said detector framing node over an optical fiber data link.

35. The image system according to claim 34, wherein the image data is communicated from said detector framing node to the second section of the host memory in groups of 512 continuous data cycles of 32 bit words starting at a single designed base address.

36. The image system according to claim 28, wherein said detector framing node receives the image data from the image detection system in real time.

37. The image system according to claim 28, wherein the image data is radioscopic image data.

38. The image system according to claim 28, wherein the host operating system is a non-real time operating system.

39. The image system according to claim 38, wherein the host operating system is a task based operating system.

40. The image system according to claim 28, wherein the host operating system is a task based operating system.

41. The image system according to claim 28, wherein the host operating system is a real time operating system.

42. The image system according to claim 28, wherein a host application running on the host processor prepares a list of physical addresses for storing the image data in the host memory, and the host application transfers the list of physical addresses to registers in said detector framing node such that said detector framing node transfers the image data to locations specified by the physical address without management by the host operating system.

43. The image system according to claim 28, wherein the second section of the host memory is divided into a plurality of buffers with the physical address of each buffer aligned on a host memory page boundary.

44. The image system according to claim 43, wherein each buffer is physically contiguous such that said detector framing node does not perform scatter-gather memory management during communication of the image data to the host memory.