Non-volatile memory device having floating trap type memory cell and method of forming the same

• US 20030030097A1
• Filed: 08/09/2002
• Published: 02/13/2003
• Est. Priority Date: 08/09/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jung-Dal, Lee, Chang-Hyun, Shin, Wang-Chul
• Granted Patent: US 6,781,193 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

Claims

1. A non-volatile semiconductor memory device comprising:

a cell gate pattern in a cell array region, a high-voltage-type gate pattern in a peripheral high-voltage region, and a low-voltage-type gate pattern in a peripheral low-voltage region on a semiconductor substrate,

wherein the high-voltage-type gate pattern includes a high-voltage gate insulating layer, a first conductive layer, a triple layer, and a second conductive layer, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer,

wherein the cell gate pattern includes the triple layer and the second conductive layer, and

wherein the low-voltage-type gate pattern includes a low-voltage gate insulating layer, the first conductive layer, the triple layer, and the second conductive layer.

2. The device as claimed in claim 1, further comprising a resistor pattern in a resist region,

wherein the resistor pattern includes at least the first conductive layer formed on an insulating layer for electrical isolation from the substrate.

3. The device as claimed in claim 2, wherein the insulating layer is a trench-type device isolation layer or the high-voltage gate insulating layer.

4. The device as claimed in claim 2, further comprising a contact plug formed over the resistor pattern wherein, the resistor pattern has a contact region including the high voltage gate insulating layer and the first conductive layer and a line region including the high-voltage gate insulating layer, the first conductive layer, the triple layer, and the second conductive layer, and

wherein the contact plug formed over the resistor pattern is isolated from the second conductive layer in the contact region.

5. The device as claimed in claim 1, wherein the cell gate pattern, the high-voltage-type gate pattern, and the low-voltage-type gate pattern have an insulating spacer on their sidewalls.

6. The device as claimed in claim 1, wherein the second conductive layer is a dual layer comprising a lower layer of polysilicon and an upper layer of metal silicide.

7. The device as claimed in claim 1, further comprising a butting contact concurrently connected to the first and second conductive layers in the respective low-and high-voltage-type gate patterns.

8. The device as claimed in claim 1, wherein a top surface elevation of the triple layer is lower than a top surface elevation of a trench-type device isolation layer formed at the substrate in a cell array region, and

wherein a bottom surface elevation of the triple layer is higher than a top surface elevation of the trench-type device isolation layer in peripheral high-and low-voltage regions.

9. The device as claimed in claim 1, wherein the second conductive layer comprises a lower conductive layer and an upper conductive layer.

10. The device as claimed in claim 9, wherein the lower conductive layer is a polysilicon layer, and the upper conductive layer is a dual layer comprising a lower layer of polysilicon and an upper layer of metal silicide.

11. The device as claimed in claim 9, wherein a top surface elevation of the lower conductive layer is lower than a top surface elevation of a device isolation layer in a cell array region and in peripheral high-and low-voltage regions.

12. A non-volatile memory device comprising a cell gate pattern of a cell array region, a high-voltage-type gate pattern of a peripheral high-voltage region, and a low-voltage-type gate pattern of a peripheral low-voltage region on a semiconductor substrate,

wherein the high-voltage-type gate pattern includes a high-voltage gate insulating layer, a first conductive layer, and a high-conductivity layer,

wherein the cell gate pattern for a memory component includes a triple layer, a second conductive layer, and the low resist conductive layer, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer, and

wherein the low-voltage-type gate pattern includes a low-voltage gate insulating layer, the first conductive layer, and the high-conductivity layer.

13. The device as claimed in claim 12, further comprising a resistor region, and a resistor pattern in the resistor region,

wherein the resistor pattern includes at least the first conductive layer that is formed on an insulating layer for electrical isolation from the substrate.

14. The device as claimed in claim 13, wherein the insulating layer is a trench-type device isolation layer or the high-voltage gate insulating layer.

15. The device as claimed in claim 13, further comprising a contact plug formed over the resistor pattern wherein, the resistor pattern has a contact region including the gate insulating layer and the first conductive layer and a line region including the gate insulating layer, the first conductive layer, the triple layer, and the second conductive layer, and

wherein the contact plug formed over the resistor pattern is isolated from the second conductive layer and the high-conductivity layer in the contact region.

16. The device as claimed in claim 12, further comprising an insulating spacer formed on sidewalls of the cell gate pattern, the high-voltage-type gate pattern, and the low-voltage-type gate pattern.

17. The device as claimed in claim 12, wherein a top surface elevation of the triple layer is lower than a top surface elevation of the trench-type device isolation layer formed at the substrate in the cell array region, and

wherein a top surface elevation of the first conductive layer is higher than a top surface elevation of the trench-type device isolation layer in the peripheral high-and low-voltage-type gate pattern regions.

18. The device as claimed in claim 19, further comprising a contact formed on the high-conductivity layer in a partial region of each of the cell gate pattern, the high-voltage-type gate pattern, and the low-voltage type gate pattern.

19. The device as claimed in claim 12, wherein the high-conductivity layer includes a metal silicide layer as the uppermost layer.

20. The device as claimed in claim 19, wherein the high-conductivity layer comprises a lower layer of polysilicon and an upper layer of metal silicide.

21. The device as claimed in claim 20, wherein in the cell array region, a top surface elevation of the trench-type device isolation layer formed over the substrate is higher than a top surface elevation of the second conductive layer and is lower than a top surface elevation of the polysilicon layer of the high-conductivity layer, and

wherein in the high-and lower-voltage-type gate pattern regions, a top surface of the trench type device isolation layer is higher than a top surface elevation of the first conductive layer and is lower than a top surface elevation of the polysilicon layer of the high-conductivity layer.

22. The device as claimed in claim 20, further comprising a resistor pattern in a resist region,

wherein the resistor pattern includes at least the first conductive layer and the polysilicon layer of the high-conductivity layer, the first conductive layer being formed on an insulating layer.

23. The device as claimed in claim 22, wherein the insulating layer is a trench-type device isolation layer or the high-voltage-type gate insulating layer.

24. The device as claimed in claim 22, wherein the resistor pattern has the high-voltage gate insulating layer, the first conductive layer, and the polysilicon layer of the high-conductivity layer.

25. The device as claimed in claim 22, wherein in the cell array region, a top surface elevation of the trench-type device isolation layer formed on the substrate is higher than a top surface elevation of the second conductive layer and is lower than a top surface elevation of the polysilicon layer of the high-conductivity layer, and

wherein in the peripheral high-and low-voltage regions, a top surface elevation of the trench-type device isolation layer is higher than a top surface elevation of the first conductive layer and is lower than a top surface elevation of the polysilicon layer of the high-conductivity layer.

26. A non-volatile memory device comprising a cell gate pattern of a cell array region, a high-voltage-type gate pattern of a peripheral high-voltage region, and a low-voltage-type gate pattern and a line-type resistor pattern of a peripheral low-voltage region,

wherein the high-voltage type gate pattern includes a high-voltage gate insulating layer, the conductive layer, a triple layer, a polysilicon layer, and a metal silicide layer, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer,

wherein the cell gate pattern for a memory component includes the triple layer, the polysilicon layer, and the metal silicide layer,

wherein the low-voltage-type gate pattern includes a low-voltage gate insulating layer, a conductive layer, the triple layer, the polysilicon layer, and the metal silicide layer,

wherein the resistor pattern has a line region and a contact region, the line region including the high-voltage gate insulating layer, the conductive layer, the triple layer, the polysilicon layer, and the metal silicide layer, and the contact region including the high-voltage gate insulating layer, and the conductive layer,

wherein in the cell array region, a top surface elevation of the triple layer is lower than a top surface elevation of a trench-type device isolation layer formed over the substrate, and

wherein in the peripheral high-and low-voltage regions, a bottom surface elevation of the triple layer is higher than a top surface elevation of the trench-type device isolation layer,

the device further comprising:

an insulating spacer formed on sidewalls of the cell gate pattern, the high-voltage-type gate pattern, the low-voltage-type gate pattern, and the resistor pattern;

a butting contact concurrently connected to the conductive layer, the polysilicon layer, and the metal silicide layer in the contact region of the respective low-voltage-type gate pattern and high-voltage-type gate pattern;

a first contact plug formed on the metal sislicide layer of the cell gate pattern; and

a second contact plug formed on the conductive layer of the contact region of the resist pattern, wherein the metal silicide layer and the polysilicon layer of the line regions is isolated from the contact plug.

27. A non-volatile memory device comprising a cell gate pattern in a cell array region, a high-voltage-type gate pattern in a peripheral high voltage region, and a low-voltage-type gate pattern and a line type resistor pattern in a peripheral low voltage region,

wherein the high-voltage-type gate pattern includes a high voltage gate insulating layer, a first conductive layer, a triple layer, a polysilicon layer, a metal silicide layer, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer,

wherein the cell gate pattern includes the triple layer, a second conductive layer, the polysilicon layer, and the metal silicide layer,

wherein the low-voltage-type gate pattern includes a low voltage gate insulating layer, a conductive layer, the triple layer, the polysilicon layer, and the metal silicide layer,

wherein the resistor pattern has a line region and a contact region, the line region including the high-voltage gate insulating layer, the first conductive layer, the triple layer the second conductive layer, the polysilicon layer, and the metal silicide layer, and the contact region including the high-voltage gate insulating layer, and the first conductive layer,

wherein in the cell gate pattern region, a top surface elevation of the triple layer is lower than a top surface elevation of a trench-type device isolation layer formed over the substrate, and

wherein in the high-and low-voltage-type gate pattern regions, a top surface elevation of the trench-type device isolation layer is higher than a top surface elevation of the second conductive layer and is lower than a top surface elevation of the polysilicon layer,

the device further comprising:

an insulating spacer formed on sidewalls of the gate pattern for a memory component, the high-voltage-type gate pattern, the low-voltage-type gate pattern, and the resistor pattern;

a butting contact plug concurrently connected to the first conductive layer, the second conductive layer, the metal silicide layer, and the polysilicon layer by removal of the metal silicide layer, the polysilicon layer, the second conductive layer, and the triple layer in a part of the contact region in the respective low-and high-voltage-type gate patterns;

a first contact plug connected to the metal silicide layer of the gate pattern for a memory component; and

another contact plug formed in the contact region of the resistor pattern, the another contact plug not being in contact with the metal silicide layer, the polysilicon layer, and the second conductive layer.

28. A method of fabricating a non-volatile semiconductor memory device, comprising:

(a) forming a device isolation layer in a substrate;

(b) forming a low-voltage gate insulating layer in at least a peripheral low-voltage region of the substrate, and forming a high-voltage-type gate insulating layer in at least a peripheral high-voltage region of the substrate;

(c) stacking a first conductive layer over substantially the entire surface of the substrate;

(d) removing the first conductive layer in a cell array region to expose the substrate; and

(e) sequentially forming a triple layer and a second conductive layer over substantially the entire surface of the exposed substrate in the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer.

29. A method of fabricating a non-volatile semiconductor memory device, comprising:

(a) forming a device isolation layer in a substrate;

(b) forming a low-voltage gate insulating layer in at least a peripheral low-voltage region of the substrate, and forming a high-voltage gate insulating layer in at least a peripheral high-voltage region of the substrate;

(c) stacking a first conductive layer over substantially the entire surface of the substrate;

(d) removing the first conductive layer in the cell array region to expose the substrate;

(e) sequentially forming a triple layer and a second conductive layer on an entire surface of the exposed substrate in the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer;

(f) patterning a substrate where the second conductive layer is formed, whereby forming a cell gate pattern in the cell array region and forming high-and low-voltage-type gate patterns in the peripheral high-and low-voltage regions, respectively;

(g) removing the second conductive layer and the triple layer of the respective high-and low-voltage-type gate patterns to form a butting region exposing the first polysilicon layer;

(h) forming and patterning an interlayer insulating layer over substantially the entire surface of the substrate to form contact holes including a butting contact hole extending over the butting region; and

(i) forming a contact plug to fill the contact hole.

30. The method as claimed in claim 29, wherein in the step (b), the gate insulating layer for a high voltage is formed in a resist region,

wherein in the step (f), a resistor pattern is formed in the resist region,

wherein in the step (g), the second conductive layer and the triple layer are removed in the contact region of the resistor pattern, and

wherein in the step (h), contact holes are formed within the contact region in the resistor pattern so that they are not connected to a high-conductivity layer.

31. The method as claimed in claim 29, further comprising forming an insulating spacer on sidewalls of the patterns.

32. The method as claimed in claim 29, wherein the second conductive layer is formed by sequentially stacking a conductive layer of silicon and another conductive layer of metal.

33. The method as claimed in claim 32, wherein in the step (a), a trench-type device isolation layer is formed in the resist region,

wherein in the step (f), a resistor pattern is formed in the resist region,

wherein in the step (g), the conductive layer of metal is removed in all regions of the conductive pattern, and

wherein in the step (h), a contact hole is formed to expose the polysilicon layer of the resistor pattern.

34. A method of fabricating a non-volatile semiconductor memory device, comprising:

(a) forming a low-voltage gate insulating layer in at least a peripheral low-voltage region of a substrate, and forming a high-voltage gate insulating layer in at least a peripheral high-voltage region of the substrate;

(b) stacking a first conductive layer on an entire surface of the substrate;

(c) removing the first conductive layer in a cell array region to expose the substrate;

(d) sequentially forming a triple layer and a second conductive layer on an entire surface of the exposed substrate in the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer;

(e) forming a trench-type device isolation layer on a substrate where the second conductive layer is formed;

(f) forming a high-conductivity layer on a substrate where the device isolation layer is formed;

(g) patterning a substrate where the high-conductivity layer is formed, whereby forming a cell gate pattern in the cell array region and forming high-and low-voltage gate patterns in the peripheral high-and low-voltage regions, respectively;

(h) removing the low resist conductive layer, the second conductive layer, and the triple layer of the respective high-and low-voltage-type gate patterns to form a butting region exposing the first polysilicon layer;

(i) forming and patterning an interlayer insulating layer on an entire surface of the substrate to form contact holes including a butting contact hole extending over the butting region; and

(j) forming a contact plug to fill the contact hole.

35. The method as claimed in claim 34, where in the step (a), the gate insulating layer is formed in a resist region,

wherein in the step (g), a resistor pattern is formed in the resist region,

wherein in the step (h), the high-conductivity layer, the second conductive layer, and the triple layer are removed in the contact region of the resistor pattern, and

wherein in the step (i), a contact hole is formed to extend over only the contact region of the resistor pattern.

36. The method as claimed in claim 34, further comprising forming an insulating spacer on each of the sidewalls of the patterns formed in the step (g).

37. The method as claimed in claim 34, wherein the high-conductivity layer is formed by sequentially stacking a conductive layer of silicon and another conductive layer of metal.

38. The method as claimed in claim 37, wherein in the step (e), a trench-type device isolation layer is formed in the resist region,

wherein in the step (f), a resistor pattern is formed in the resist region,

wherein in the step (g), the conductive layer of metal is removed in all regions of the conductive pattern, and

wherein in the step (h), a contact hole is formed to expose the polysilicon layer of the resistor pattern.

39. A method of fabricating a non-volatile semiconductor memory device, comprising:

(a) forming a device isolation layer in a substrate;

(b) forming a low-voltage-type gate insulating layer in at least a peripheral low-voltage region of the substrate, and forming a high-voltage type gate insulating layer in at least a peripheral high-voltage region of the substrate;

(c) stacking a first conductive layer on an entire surface of the substrate;

(d) removing the first conductive layer in the cell array region to expose the substrate;

(e) sequentially forming a triple layer and a second conductive layer over substantially the entire surface of the exposed substrate in the cell array region, the triple layer including a tunneling insulating layer, a charge-storage layer, and a blocking insulating layer;

(f) patterning a substrate where the second conductive layer is formed, thereby removing the second conductive layer and the triple layer in a removal region including the peripheral low-and high-voltage regions;

(g) forming a high-conductivity layer on an entire surface of the substrate; and

(h) patterning a substrate where the second conductive layer is formed, whereby forming a cell gate pattern in the cell array region and forming high-and low-voltage-type gate patterns in the peripheral high-and low-voltage regions, respectively.

40. The method as claimed in claim 39, further comprising:

(i) forming and patterning an interlayer insulating layer over the substantially the entire surface of the substrate to form contact holes including contact holes exposing the high-conductivity layer; and

(j) forming a contact plug to fill the contact hole.

41. The method as claimed in claim 40, wherein in the step (a), a device isolation layer is formed in a resist region,

wherein in the step (h), a resistor pattern is formed in the resist region,

wherein the low resist conductive layer, the second conductive layer, and the triple layer are removed in the contact region of the resistor pattern prior to formation of the interlayer insulating layer, and

wherein in the step (i), a contact hole is formed to extend over only the contact region of the resistor pattern in the resist region.

42. The method as claimed in claim 40, wherein the removal region includes a resist region,

wherein in the step (h), a resistor pattern is formed in the resist region,

wherein the high-conductivity layer is removed in all regions of the resistor pattern prior to formation of the interlayer insulating layer, and

wherein in the step (i), a contact hole is formed in the resist region to expose the first conductive layer.

43. A method of fabricating a non-volatile semiconductor memory device, comprising:

(a) forming a low-voltage gate insulating layer in at least a peripheral low-voltage region of the substrate, and forming a high-voltage-type gate insulating layer in at least a peripheral high-voltage region of the substrate;

(b) stacking a first conductive layer on an entire surface of the substrate;

(c) removing the first conductive layer in the cell array region to expose the substrate;

(d) sequentially forming a triple layer and a second conductive layer over substantially the entire surface of the exposed substrate in the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer;

(e) patterning a substrate where the second conductive layer is formed, whereby removing the second conductive layer and the triple layer in a removal region including the peripheral low-and high-voltage regions;

(f) forming a trench type device isolation layer in a substrate undergoing the step (e);

(g) forming a high-conductivity layer over substantially the entire surface of the substrate where the device isolation layer is formed;

(h) patterning the substrate where the low resist conductive layer is formed, thereby forming a cell gate pattern in the cell array region and forming high-and low-voltage-type gate patterns in the peripheral high-and low-voltage regions, respectively.

(i) forming and patterning an interlayer insulating layer on an entire surface of the substrate to form contact holes including contact holes exposing the high-conductivity layer; and

(j) forming a contact plug to fill the contact hole.

44. The method as claimed in claim 43, wherein in the step (a), the gate insulating layer is formed in a resist region,

wherein in the step (h), a resistor pattern is formed in the resist region,

wherein the high-conductivity layer, the second conductive layer, and the triple layer are removed in the contact region of the resistor pattern prior to formation of the interlayer insulating layer, and

wherein in the step (i), only a contact hole stretching over the contact region of the resistor pattern is formed in the resist region.

45. The method as claimed in claim 43, further comprising forming an insulating spacer on sidewalls of the patterns formed in the step (h).

46. The method as claimed in claim 43, wherein the low-resist conducive layer is formed by sequentially stacking a conductive layer of silicon and another conductive layer of metal.

47. The method as claimed in claim 46, wherein in the step (f), a device isolation layer is formed in a resist region,

wherein in the step (h), a resistor pattern comprising the high-conductivity layer is formed in the resist region,

wherein a metal-containing conductive layer is removed in all regions of the resistor pattern prior to formation of the interlayer insulating layer, and

wherein in the step (i), a contact hole is formed in the resist region to expose the polysilicon.

48. The method as claimed in claim 43, wherein the removal region includes a resist region,

wherein in the step (h), a resistor pattern is formed in the resist region,

wherein the high-conductivity layer is removed in all regions of the resistor pattern prior to formation of the interlayer insulating layer, and

wherein in the step (i), a contact hole is formed in the resist region to expose the first conductive layer.