Trench MIS device with graduated gate oxide layer

• US 20030030104A1
• Filed: 03/26/2002
• Published: 02/13/2003
• Est. Priority Date: 08/10/2001
• Status: Active Grant

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Terrill, Kyle, Chen, Kuo-In, Darwish, Mohamed N., Lui, Kam Hong, Pattanayak, Deva N., Yue, Christiana, Giles, Frederick P.
• Granted Patent: US 6,903,412 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the body and drain regions intersects the trench in the transition region. This structure allows for a greater margin of error in the placement of the PN junction during the manufacture of the device, since the intersection between the PN junction can be located anywhere in the transition region. The MIS device also has improved breakdown characteristics.

Claims

1. A metal-insulator-semiconductor (MIS) device comprising:

a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;

a drain region of a first conductivity type; and

a body region of a second conductivity type opposite to said first conductivity type adjacent to at least a portion of a sidewall of said trench;

wherein said trench is lined with an oxide layer, said oxide layer comprising a first section, a second section and a transition region between said first and second sections, said first section being adjacent at least a portion of said drain region, said second section being adjacent at least a portion of said body region, a thickness of said oxide layer in said first section being greater than a thickness of said oxide layer in said second section, a thickness of said oxide layer in said transition region decreasing gradually from said first section to said second section, a PN junction between said body region and said drain region terminating at said trench adjacent said transition region of said oxide layer.

2. The MIS device of claim 1 wherein said transition region is located adjacent a bottom surface of said trench.

3. The MIS device of claim 1 wherein said transition region is located adjacent a sidewall of said trench.

4. The MIS device of claim 1 wherein said transition region is located adjacent a corner of said trench.

5. The MIS device of claim 1 further comprising a source region located adjacent a top surface, said trench and said body region.

6. The MIS device of claim 1 wherein said body region is P-type and said drain region is N-type.

7. The MIS device of claim 1 comprising a highly doped region of said first conductivity type adjacent a bottom of said trench, said highly doped region having a doping concentration greater than a doping concentration of said drain.

8. A semiconductor device comprising:

a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;

a first region of a first conductivity type adjacent to at least a portion of a bottom of said trench; and

a second region of a second conductivity type opposite to said first conductivity type adjacent to at least a portion of a sidewall of said trench; and

wherein said trench is lined with an oxide layer, said oxide layer comprising a first section, a second section and a transition region between said first and second sections, said first section being adjacent at least a portion of said first region of said semiconductor device, said second section being adjacent at least a portion of said second region of said semiconductor device, a thickness of said oxide layer in said first section being greater than a thickness of said oxide layer in said second section, a thickness of said oxide layer in said transition region decreasing gradually from said first section to said second section, a PN junction between said first region and said second region terminating at said trench adjacent said transition region of said oxide layer.