Apparatus and methods for testing circuit boards

• US 20030030459A1
• Filed: 08/10/2001
• Published: 02/13/2003
• Est. Priority Date: 08/10/2001
• Status: Active Grant

• Current Assignee: James Sabey
• Original Assignee: James Sabey
• Inventors: Sabey, James
• Granted Patent: US 6,734,681 B2
• Time in Patent Office: Days
• US Class Current: 324/761
• CPC Class Codes: G01R 31/2805 Bare printed circuit boards

Abstract

Methods and apparatus are disclosed for detecting manufacturing defects on unpopulated printed circuit boards under test (BUT) utilizing reliable single point current measurement. In a first set of preferred embodiments, an AC signal generator is connected to a signal plate placed under the BUT for applying an electrical field and thereby generating signals in conductors of the BUT. An array of pins mounted on an assembly on top of the BUT at fixed intervals samples currents from the test points on the BUT. In a second set of preferred embodiments, the AC signal generator is connected to the pin array, and the pins apply test signals into the conductive elements of the BUT at fixed intervals. The signal plate detects the electrical field on the BUT. The detected signals are analyzed to discern board faults.

Claims

1. A method for testing and assessing an unpopulated printed circuit board under test (BUT), the BUT having electrically conductive paths and surfaces, the method for testing the electrical and physical continuity of the paths and surfaces and for testing conformance of the BUT to a known standard, the method comprising the steps of:

(a) providing an alternating test signal at a first side of the BUT for radiating an electrical field, via a plate, onto the BUT, the field inducing currents and charges on the BUT'"'"'s electrically conductive paths and surfaces;

(b) detecting currents via a plurality of pins at a second side of the BUT from the conductive surfaces of the BUT, wherein relative movement between the BUT and the pins produces multiple current measurements of the BUT test points;

(c) moving one of either the plurality of pins or the BUT;

(d) converting the detected currents to digital data; and

(e) analyzing the digital data to assess the BUT.

2. The method of claim 1 wherein the plate is movable and the pins are stationary.

3. The method of claim 1 wherein the pins are movable and the plate is stationary.

4. The method in claim 3 wherein the pins are moved by an X-Y table.

5. The method of claim 1, wherein the converting step receives a signal from each test point, measures a value of the signal, and converts the analog values to form the digital data, and wherein the analyzing step diagnoses faults on the BUT based upon the digital data.

6. A method for testing and assessing an unpopulated printed circuit board under test (BUT), the BUT having electrically conductive paths and surfaces, the method for testing the electrical and physical continuity of the paths and surfaces and for testing conformance of the BUT to a known standard, the method comprising the steps of:

(a) providing an alternating test signal at a first side of the BUT via a plurality of pins for generating currents on the BUT'"'"'s electrically conductive paths and surfaces;

(b) detecting an electrical field via a plate at a second side of the BUT, wherein relative movement between the BUT and the pins produces multiple field measurements of the BUT;

(c) moving one of either the plurality of pins or the BUT;

(d) converting the detected fields to digital data; and

(e) analyzing the digital data to assess the BUT.

7. The method of claim 6 wherein the plate is movable and the pins are stationary.

8. The method of claim 6 wherein the pins are movable and the plate is stationary.

9. The method in claim 8 wherein the pins are moved by an X-Y table.

10. A device for testing an unpopulated printed circuit board under test (BUT) having electrically conductive paths and surfaces whose electrical and physical continuity and conformance to a known standard is to be verified, the device comprising:

a signal plate adjacent to the BUT;

a signal generator for providing an alternating test signal to the signal plate;

wherein the signal plate radiates an electric field onto the BUT according to the test signal, and wherein the electric field induces currents and charges on the BUT'"'"'s electrically conductive paths and surfaces;

a pin array assembly (PAA) adjacent to the BUT for detecting the signals induced on the BUT'"'"'s electrically conductive paths and surfaces, wherein each relative movement between the BUT and the PAA produces signal measurements of BUT test points;

a selector to provide isolation between the pins of the array assembly;

a moving mechanism for moving the PAA relative to the BUT;

a digital signal processor for converting the detected signals to digital data;

a computer for controlling the relative pin array assembly movements, sequencing the selector, storing digital data from the digital signal processor, and analyzing the digital data.

11. The apparatus in claim 10 wherein said AC signal generator is one of either amplitude modulated or frequency modulated.

12. The apparatus in claim 10 wherein said PAA comprises a large, one dimensional array spaced in a predetermined configuration.

13. The apparatus of claim 10 wherein said PAA comprises a large two dimensional array spaced in a predetermine configuration.

14. The apparatus of claim 10 wherein the computer includes a work station running software to diagnose faults on the BUT and wherein said computer analysis receives a signal from each test point and measures an analog value of the signal, converts the analog value to digital form, and transfers the digital form to the work station.

15. The apparatus of claim 10 wherein the PAA pins consist of a conductive fiber.

16. The apparatus of claim 10 wherein the PAA and the signal plate are disposed on opposite sides of the BUT.

17. A device for testing an unpopulated printed circuit board under test (BUT) having electrically conductive paths and surfaces whose electrical and physical continuity and conformance to a known standard is to be verified, the device comprising:

a pin array assembly (PAA) adjacent to the BUT;

a signal generator for providing an alternating test signal to the PAA;

wherein the PAA generates currents on the BUT'"'"'s electrically conductive paths and surfaces according to the test signal;

a signal plate adjacent to the BUT for detecting an electrical field of the BUT and generating output signals based upon the detected field, the signal plate having an insulating layer between the signal plate and the BUT;

wherein each relative movement between the BUT and the PAA produces a field measurement of the BUT;

a selector to provide isolation between the pins of the array assembly;

a moving mechanism for moving the BUT relative to the PAA;

a digital signal processor for converting the output signals to digital data; and

a computer for controlling the pin array assembly movements, sequencing the selector, storing digital data from the digital signal processor, and analyzing the digital data.

18. The apparatus in claim 17 wherein said AC signal generator is one of either amplitude modulated or frequency modulated.

19. The apparatus in claim 17 wherein said PAA comprises a large, one dimensional array spaced in a predetermined configuration.

20. The apparatus of claim 17 wherein said PAA comprises a large two dimensional array spaced in a predetermine configuration.

21. The apparatus of claim 17 wherein the computer includes a work station running software to diagnose faults on the BUT.

22. The apparatus of claim 17 wherein a broadband amplifier with input selectors is used to generate low impedance at the pins.

23. The apparatus of claim 17 wherein the PAA pins consist of a conductive fiber.