Modulator for digital amplifier
First Claim
Patent Images
1. A restricted modulation method comprising the steps of:
- receiving an input signal that alternates between first and second states;
storing the input signal and providing the stored input signal as an output signal;
monitoring the received input signal to measure a) an amount of time for each state in the input signal to provide a pulse width value and b) an amount of time between successive changes from one of the first and second states to the other one of the first and second states to provide a pulse period value;
substituting the output signal for the input signal if the pulse width value is less than a first predetermined value or if the pulse period value is less than a second predetermined value;
substituting an inverted output signal for the input signal if the pulse width value is greater than a third predetermined value.
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Abstract
A digital modulator for driving a digital amplifier. The digital modulator has a subtractor which receives a digital input signal. A filter amplifier receives the output of the filter amplifier and is tuned to an idle frequency of the digital modulator. The digital modulator includes a delay element and a digital comparator. The digital comparator receives the output from the filter and applies it to the delay element. A feedback loop couples the output of the delay element to the subtractor.
56 Citations
4 Claims
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1. A restricted modulation method comprising the steps of:
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receiving an input signal that alternates between first and second states;
storing the input signal and providing the stored input signal as an output signal;
monitoring the received input signal to measure a) an amount of time for each state in the input signal to provide a pulse width value and b) an amount of time between successive changes from one of the first and second states to the other one of the first and second states to provide a pulse period value;
substituting the output signal for the input signal if the pulse width value is less than a first predetermined value or if the pulse period value is less than a second predetermined value;
substituting an inverted output signal for the input signal if the pulse width value is greater than a third predetermined value.
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2. A restricted modulator comprising:
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a terminal which is configured to receive an input signal that alternates between first and second states;
a delay element which stores the input signal and provides the stored input signal as an output signal;
first and second counters which count pulses of a clock signal to measure a) an amount of time for each state in the input signal to provide a pulse width value and b) an amount of time between successive changes from one of the first and second states to the other one of the first and second states to provide a pulse period value;
a multiplexer that substitutes the output signal for the input signal if the pulse width value is less than a first predetermined value or if the pulse period value is less than a second predetermined value and that substitutes an inverted output signal for the input signal if the pulse width value is greater than a third predetermined value.
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3. A restricted modulator coupled to receive an input signal and to provide a modulated output signal, the restricted modulator comprising:
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a first multiplexer having an output port, a first signal input port coupled to receive the input signal of the restricted modulator and a second signal s input port coupled to receive the output signal, wherein the first multiplexer is responsive to a first control signal for selectively coupling the output port to one of the first and second input ports;
a second multiplexer, having an output port, a first input port coupled to receive an inverted version of the output signal of the modulator and a second input port coupled to the output port of the first multiplexer, wherein the second multiplexer is responsive to a second control signal for selectively coupling the output port of the second multiplexer to one of the first and second input ports of the second multiplexer;
a delay element, having a clock signal input port, a signal input port coupled to the output port of the second multiplexer and an output port which provides the output signal of the restricted modulator;
circuitry, coupled to the delay element for providing a difference pulse signal when a signal applied to the input port of the delay element differs from the output signal of the modulator;
a first counter, coupled to receive the clock signal and the difference pulse signal for generating a count value equal to a number of pulses of the clock signal between successive pulses of the difference pulse signal;
a second counter, coupled to receive the clock signal and the count value provided by the first counter, for loading the count value from the first counter responsive to a pulse of the difference signal and for incrementing its count value by one for each pulse of thc clock signal until a next pulse of the difference signal;
reference circuitry coupled to receive the count value and the incremented count value for generating the first and second control signals, the first control signal being generated when the count value is less than a first reference value or when the incremented count value is less than a second reference value and the second control signal being generated when the count value is greater than a third predetermined value.
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4. A digital modulator coupled to receive a digital input signal for driving a digital amplifier, the modulator comprising:
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a subtractor having a first signal input port coupled to receive the digital input signal, a second signal input port coupled to receive a feedback signal, and an output port;
a digital filter amplifier having an input port coupled to the output port of the subtractor and an output port, the filter being tuned to an idle frequency of the digital modulator;
a delay element;
a digital comparator for receiving the filtered output of the filter and for applying the filtered output signal to the delay element;
wherein the delay element is coupled to the subtractor for providing a signal from the output of the delay element to the second input port of the subtractor.
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Specification