Silicon on insulator DRAM process utilizing both fully and partially depleted devices

• US 20030032262A1
• Filed: 10/07/2002
• Published: 02/13/2003
• Est. Priority Date: 08/29/2000
• Status: Active Grant

• Current Assignee: Charles H. Dennison, John K. Zahurak
• Original Assignee: Charles H. Dennison, John K. Zahurak
• Inventors: Dennison, Charles H., Zahurak, John K.
• Granted Patent: US 6,818,496 B2
• Time in Patent Office: Days
• US Class Current: 438/459
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor

Abstract

This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.

Claims

1. A method of forming a semiconductor device, comprising:

thinning an upper silicon layer in at least one region of a silicon-on-insulator substrate by removing a portion of said upper silicon layer at said region; and

forming at least one partially depleted region and at least one fully depleted region in said upper silicon layer, said at least one fully depleted region being formed at said region where said portion of said upper silicon layer has been removed.

2. The method of claim 1, wherein said portion of upper silicon layer is removed by:

forming a non-oxidizable layer over said upper silicon layer;

removing at least one portion of said non-oxidizable layer to expose a portion of said upper silicon layer;

oxidizing said exposed portion of said upper silicon layer; and

removing said oxidized portion of said upper silicon layer.

3. The method of claim 2, wherein said act of forming at least one partially depleted region and at least one fully depleted region comprises:

implanting said upper silicon layer to form said at least one fully depleted region in said upper silicon layer where said oxidized portion was removed and to form said at least one partially depleted region where said upper silicon layer was not exposed.

4. The method of claim 3, wherein the acts of forming and removing a portion of said non-oxidizable layer comprise:

forming an insulating layer over said upper silicon layer;

forming a nitride layer over said insulating layer; and

removing a portion of said nitride layer and said underlying insulating layer to expose said portion of said upper silicon layer.

5. The method of claim 1, further comprising forming at least one access transistor of a memory array over said fully depleted region and forming at least one periphery device transistor over said partially depleted region.

6. The method of claim 5, further comprising forming at least one periphery device transistor over said fully depleted region.

7. The method of claim 5, wherein said at least one access transistor and said at least one periphery device transistor are part of a memory device circuit.

8. The method of claim 1, wherein said provided upper silicon layer has an initial thickness of approximately 200 nm prior to said thinning of said layer.

9. The method of claim 1, wherein said fully depleted region of said upper silicon layer is no more than 100 nm thick.

10. The method of claim 1, wherein said partially depleted region of said upper silicon layer is between about 100 nm and about 200 nm thick.

11. The method of claim 3, wherein said implanting is performed using Boron ions.

12. The method of claim 4, further comprising forming at least one access transistor of a memory array over said fully depleted region and forming at least one periphery device transistor over said partially depleted region.

13. The method of claim 12, wherein said at least one access transistor and said at least one periphery device transistor are part of a memory device circuit.

14. The method of claim 4, wherein said insulating layer is a stress absorbing layer.

15. The method of claim 14, wherein said stress absorbing layer is an oxide layer.

16. The method of claim 15, wherein said oxide layer has a thickness of about 90 Angstroms and said nitride layer has a thickness in the range of about 100-2000 Angstroms.

17. The method of claim 2, wherein said upper silicon layer is oxidized to a thickness of at least 100 nm.

18. The method of claim 2, wherein said upper silicon layer has a thickness not greater than 100 nm where said oxidized portion is removed.

19. A method of forming a semiconductor device, comprising:

forming at least one partially depleted low-threshold voltage gate device and at least one fully depleted high-threshold voltage gate device over an upper silicon layer of a silicon-on-insulator substrate, said at least one fully depleted high-threshold gate device being formed over a region of said upper silicon layer that has been thinned by removing a portion of said upper silicon layer.

20. The method of claim 19, wherein said portion of upper silicon layer is removed by:

forming a non-oxidizable layer over said upper silicon layer;

removing at least one portion of said non-oxidizable layer to expose a portion of said upper silicon layer;

oxidizing said exposed portion of said upper silicon layer; and

removing said oxidized portion of said upper silicon layer.

21. The method of claim 20, wherein said act of forming said at least one partially depleted low-threshold voltage gate device and at least one fully depleted high-threshold voltage gate device comprises:

implanting said upper silicon layer to form a fully depleted region in said upper silicon layer where said oxidized portion was removed and a partially depleted region where said upper silicon layer was not exposed.

22. The method of claim 21, wherein the acts of forming and removing a portion of said non-oxidizable layer comprise:

forming an insulating layer over said upper silicon layer;

forming a nitride layer over said insulating layer; and

removing a portion of said nitride layer and said underlying insulating layer to expose said portion of said upper silicon layer.

23. The method of claim 19, wherein said high-threshold voltage gate device is of an access transistor of a memory array over said fully depleted region and said low-threshold voltage gate device is of a periphery device transistor over said partially depleted region.

24. The method of claim 23, wherein said access transistor and said periphery device transistor are part of a memory device.

25. The method of claim 19, wherein provided said upper silicon layer has an initial thickness of approximately 200 nm prior to said thinning of said layer.

26. The method of claim 19, wherein said region of said upper silicon layer under said fully depleted high-threshold voltage gate device is no more than 100 nm thick.

27. The method of claim 19, wherein region of said upper silicon layer under said partially depleted low-threshold voltage gate device is between about 100 nm and about 200 nm thick.

28. The method of claim 21, wherein said implanting is performed using Boron ions.

29. The method of claim 22, wherein said high-threshold gate is of an access transistor of a memory array over said fully depleted region and said low-threshold gate is of a periphery device transistor over said partially depleted region.

30. The method of claim 29, wherein said access transistor and said periphery device transistor are part of a memory device circuit.

31. The method of claim 22, wherein said insulating layer is a stress absorbing layer.

32. The method of claim 31, wherein said stress absorbing layer is an oxide layer.

33. The method of claim 32, wherein said oxide layer has a thickness of about 90 Angstroms and said nitride layer has a thickness in the range of about 100-2000 Angstroms.

34. The method of claim 20, wherein said upper silicon layer is oxidized to a thickness of at least 100 nm.

35. The method of claim 20, wherein said upper silicon layer has a thickness not greater than 100 nm where said oxidized portion is removed.

36. A method of forming a memory device, comprising:

forming at least one partially depleted region and at least one frilly depleted region in an upper silicon layer of a silicon-on-insulator substrate, said at least one fully depleted region being formed in a region of said upper silicon layer that has been thinned by removing a portion of said upper silicon layer; and

forming an access transistor of a memory cell over said fully depleted region of said upper silicon layer and forming a periphery device transistor over said partially depleted region of said upper silicon layer.

37. The method of claim 36, wherein said act of thinning comprises:

forming a non-oxidizable layer over said upper silicon layer;

removing at least a portion of said non-oxidizable layer to expose a portion of said upper silicon layer;

oxidizing said exposed portion of said upper silicon layer; and

removing said oxidized portion of said upper silicon layer.

38. The method of claim 37, wherein the act of forming said at least one partially depleted region and at least one fully depleted region comprises:

implanting said upper silicon layer to form said at least one partially depleted region in said upper silicon layer where said upper silicon layer was not exposed and said at least one fully depleted region in said upper silicon layer where said oxidized portion was removed.

39. The method of claim 38, wherein the acts of forming and removing a portion of said non-oxidizable layer comprise:

forming an insulating layer over said upper silicon layer;

forming a nitride layer over said insulating layer; and

removing a portion of said nitride layer and said underlying insulating layer to expose said portion of said upper silicon layer.

40. The method of claim 36, wherein said upper silicon layer has an initial thickness of approximately 200 nm prior to said thinning of said layer.

41. The method of claim 36, wherein said fully depleted region of said upper silicon layer is no more than 100 nm thick.

42. The method of claim 36, wherein said partially depleted region of said upper silicon layer is between about 100 nm and about 200 nm thick.

43. The method of claim 38, wherein implanting is performed using Boron ions.

44. The method of claim 39, wherein said insulating layer is a stress absorbing layer.

45. The method of claim 44, wherein said stress absorbing layer is an oxide layer.

46. The method of claim 45, wherein said oxide layer has a thickness of about 90 Angstroms and said nitride layer has a thickness in the range of about 100-2000 Angstroms.

47. The method of claim 37, wherein said upper silicon layer is oxidized to a thickness of at least 100 nm.

48. The method of claim 37, wherein said upper silicon layer has a thickness not greater than 100 nm where said oxidized portion is removed.

49. A method of forming a DRAM chip, comprising:

forming at least one partially depleted region and at least one fully depleted region in an upper silicon layer of a silicon-on-insulator substrate, said at least one fully depleted region being formed in region of said upper silicon layer that has been thinned by removing a portion of said upper silicon layer;

forming an access transistor of a DRAM memory device over said fully depleted region; and

forming a periphery device transistor of said DRAM device over said partially depleted region.

50. The method of claim 49, further comprising forming a periphery device transistor of said DRAM device over said fully depleted region.

51. The method of claim 49, further comprising:

forming a non-oxidizable layer over said upper silicon layer;

removing at least a portion of said non-oxidizable layer to expose a portion of said upper silicon layer;

oxidizing said exposed portion of said upper silicon layer; and

removing said oxidized portion of said upper silicon layer.

52. The method of claim 51, wherein said act of forming said at least one partially depleted region and at least one fully depleted region comprises:

implanting said upper silicon layer to form said at least one partially depleted region in said upper silicon layer where said upper silicon layer was not exposed and said at least one fully depleted region in said upper silicon layer where said oxidized portion was removed.

53. The method of claim 52, wherein said acts of forming and removing a portion of said non-oxidizable layer comprise:

forming an insulating layer over said upper silicon layer;

forming a nitride layer over said insulating layer; and

removing a portion of said nitride layer and said underlying insulating layer to expose said portion of said upper silicon layer.

54. The method of claim 49, wherein said upper silicon layer has an initial thickness of approximately 200 nm prior to said thinning of said layer.

55. The method of claim 49, wherein said fully depleted region of said upper silicon layer is no more than 100 nm thick.

56. The method of claim 49, wherein said partially depleted region of said upper silicon layer is between about 100 nm and about 200 nm thick.

57. The method of claim 52, wherein implanting is performed using Boron ions.

58. The method of claim 53, wherein said insulating layer is a stress absorbing layer.

59. The method of claim 58, wherein said stress absorbing layer is an oxide layer.

60. The method of claim 59, wherein said oxide layer has a thickness of about 90 Angstroms and said nitride layer has a thickness in the range of about 100-2000 Angstroms.

61. The method of claim 51, wherein said upper silicon layer is oxidized to a thickness of at least 100 nm.

62. The method of claim 51, wherein said upper silicon layer has a thickness not greater than 100 nm where said oxidized portion is removed.

63. A method of forming a semiconductor device, comprising:

providing a silicon-on-insulator substrate having an upper silicon layer having a thickness suitable for forming a partially depleted region;

forming an oxide layer over said upper silicon layer;

forming a nitride layer over said oxide layer;

removing at least a portion of said nitride layer and said oxide layer to expose a portion of said upper silicon layer;

oxidizing said portion of said upper silicon layer to a thickness of at least 100 nm;

removing said oxidized portion of said upper silicon layer to thin said upper silicon layer;

implanting said upper silicon layer with a dopant to form at least one partially depleted region in said upper silicon layer where said upper silicon layer was not exposed and at least one filly depleted region in said upper silicon layer where said oxidized portion was removed;

forming at least one access transistor of a memory cell over said fully depleted region; and

forming at least one periphery device transistor over said partially depleted region.

64. The method of claim 63, wherein said implanting is performed using Boron ions.

65. The method of claim 63, wherein said oxide layer has a thickness of about 90 Angstroms and said nitride layer has a thickness in the range of about 100-2000 Angstroms.

66. The method of claim 63, wherein said semiconductor device includes a DRAM.

67. A method of forming a semiconductor device, comprising:

selectively oxidizing a silicon layer of a silicon-on-insulator substrate to form an oxide region and a non-oxidized region on the surface of said silicon layer;

removing the oxide from said oxide region to thin said silicon layer in said oxide region, thereby forming thinned regions and non-thinned regions of said silicon layer; and

placing a dopant in said silicon layer to form a fully depleted region in said thinned region of silicon layer and a partially depleted region in said non-thinned region of silicon layer.

68. A method of forming a semiconductor device, comprising:

selectively thinning a silicon layer of a silicon-on-insulator substrate to form a thinned region and a non-thinned region; and

placing a dopant into said silicon layer to form a fully depleted region in said thinned region of silicon layer and a partially depleted region in said non-thinned region of silicon layer.

69. A method of forming a semiconductor device, comprising:

processing a silicon layer of a silicon-on-insulator substrate to produce a first and a second region having different thicknesses; and

placing a dopant into said silicon layer to form a filly depleted region where said silicon layer has a smaller thickness and a partially depleted region where said silicon layer has a larger thickness.

70. A semiconductor device, comprising:

a silicon-on-insulator substrate having an upper silicon layer;

at least one partially depleted transistor over a first region of said upper silicon layer having a first thickness; and

at least one fully depleted transistor over a second region of said upper silicon layer having a thickness less than said first thickness.

71. The semiconductor device of claim 70, wherein said second region has a thickness not greater than about 100 nm.

72. The semiconductor device of claim 70, wherein said first region has a thickness between about 100 nm and about 200 nm.

73. The semiconductor device of claim 70, wherein said fully depleted transistor and said partially depleted transistor are part of a memory device circuit.

74. The semiconductor device of claim 70, further comprising a near fully depleted transistor.

75. A semiconductor device, comprising:

a silicon-on-insulator substrate having an upper silicon layer;

at least one fully depleted device formed over a portion of said upper silicon layer that has a thickness not greater than 100 nm and at least one partially depleted device formed over a portion of said upper silicon layer that has a thickness between about 100 nm to about 200 nm.

76. The semiconductor device of claim 75, wherein said fully depleted device and said partially depleted device are part of a memory device circuit.

77. The semiconductor device of claim 75, further comprising a near fully depleted device.

78. A memory device, comprising:

a silicon-on-insulator substrate having an upper silicon layer;

at least one partially depleted transistor over a first region of said upper silicon layer having a first thickness; and

at least one fully depleted transistor over a second region of said upper silicon layer having a thickness less than said first thickness.

79. The memory device of claim 78, wherein said first region has a thickness between about 100 nm and about 200 nm.

80. The memory device of claim 78, wherein said second region has a thickness not greater than about 100 nm.

81. The memory device of claim 78, wherein said partially depleted transistor and said fully depleted transistor are part of a memory device circuit.

82. The memory device of claim 78, further comprising a SRAM.

83. The memory device of claim 78, further comprising a near fully depleted transistor.

84. The memory device of claim 78, further comprising a DRAM.

85. A processor system, comprising:

a processor; and

a memory circuit coupled to said processor, at least one of said processor and memory circuit comprising a silicon-on-insulator substrate having an upper silicon layer with at least one partially depleted transistor over a first region of said upper silicon layer having a first thickness, and at least one fully depleted transistor over a second region of said upper silicon layer having a thickness less than said first thickness.

86. The processor system of claim 85, wherein said at least one fully depleted transistor and said at least one partially depleted transistor are part of a memory device circuit.

87. The processor system of claim 85, wherein said second region of said upper silicon layer has a thickness not greater than 100 nm.

88. The processor system of claim 85, wherein said first thickness is between about 100 nm and about 200 nm.

89. The processor system of claim 85, further comprising a nearly depleted transistor.

90. The processor system of claim 85, wherein said silicon-on-insulator substrate having said upper silicon layer with said fully depleted and partially depleted regions is part of a memory device.

91. The processor system of claim 85, wherein said silicon-on-insulator substrate having said upper silicon layer with said fully depleted and partially depleted regions is part of said processor.

92. The processor system of claim 85, wherein said processor and said memory circuit are integrated on a single chip.