Method for forming a metallization layer

• US 20030032279A1
• Filed: 08/13/2002
• Published: 02/13/2003
• Est. Priority Date: 06/03/1996
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yu, Chris Chang, Sandhu, Gurtej Singh
• Granted Patent: US 7,189,317 B2
• Time in Patent Office: Days
• US Class Current: 438/629
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1078 Multiple stacked thin films not being formed in openings in dielectrics
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier

Abstract

A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. The first and second layers are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.

Claims

1. A method for forming a metallization layer outwardly from a semiconductor substrate, the method comprising the steps of:

forming a first layer of a material outwardly from the semiconductor substrate;

forming contact vias that extend through the first layer to the semiconductor substrate;

forming a layer of a second material outwardly from the first layer;

selectively removing portions of the second layer such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias;

placing the first and second layers at different surface potentials;

electro-depositing the first and second layers in a solution of metal ions by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle, the voltage and surface potentials selected such that the metal is deposited on the remaining portions of the second layer and that metal deposited on the first layer during a positive duty cycle is removed from the first layer during a negative duty cycle; and

selectively removing exposed portions of the first layer.

2. The method of claim 1, wherein the step of depositing a first layer comprises depositing a layer of poly-silicon outwardly from the semiconductor substrate.

3. The method of claim 1, wherein the step of electroplating comprises the steps of:

depositing the semiconductor substrate in an electrolytic bath containing a metal having a reduction potential; and

exposing the bath to a modulated voltage such that during a positive duty cycle the metal is deposited on exposed surfaces of the first layer and the second layer and that during a negative duty cycle the metal is removed from the exposed surface of the first layer.

4. The method of claim 1, wherein the step of depositing a second layer comprises depositing a layer of titanium nitride.

5. The method of claim 3, wherein the step of depositing the semiconductor substrate in an electrolytic bath comprises the step of depositing the semiconductor substrate in an electrolytic bath containing copper ions.

6. The method of claim 1, wherein the step of placing the first and second layers at different surface potentials comprises the step of applying a first voltage to a surface of the first layer and applying a second voltage, different than the first voltage, to the second layer, wherein the first and second layers are separated by an insulating layer.

7. The method of claim 1, wherein the step of placing the first and second layers at different surface potentials comprises the step of selecting a material for the first layer that has an innate surface potential that is less than the innate surface potential for the material selected for the second layer.

8. The method of claim 1, wherein the step of electroplating the first and second surfaces comprises the step of electroplating the first and second surfaces with a voltage source that produces a substantially square wave voltage output.

9. A method for forming a metallization layer outwardly from a semiconductor substrate, the method comprising the steps of:

forming a first layer of a material outwardly from the semiconductor substrate, the first layer having a first innate surface potential;

forming contact vias that extend through the first layer to the semiconductor substrate;

forming a layer of a second material outwardly from the first layer so as to line the contact vias and cover the first layer, the second layer having a second innate surface potential different from said first innate surface potential;

selectively removing portions of the second layer such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias;

placing the semiconductor substrate with the first and second layers in an electrolytic bath comprising a solution of metal ions;

applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the electrolytic bath, the voltage and surface potentials selected such that the metal is deposited on the remaining portions of the second layer and that metal deposited on the first layer during a positive duty cycle is removed from the first layer during a negative duty cycle; and

selectively removing exposed portions of the first layer.

10. The method of claim 9, wherein the step of depositing a first layer comprises depositing a layer of poly-silicon outwardly from the semiconductor substrate.

11. The method of claim 9, wherein the step of placing the semiconductor substrate with the first and second layers in an electrolytic bath comprises the step of placing the semiconductor substrate with the first and second layers in an electrolytic bath containing copper ions in solution.

12. The method of claim 9, wherein the step of depositing a second layer comprises depositing a layer of titanium nitride.

13. The method of claim 9, and further comprising the step of imposing an external voltage to one of the first and second layers to place the first and second layers at different surface potentials.

14. The method of claim 9, and further comprising the step of placing the first and second layers at different surface potentials by applying a first voltage to a surface of the first layer and applying a second voltage, different from the first voltage, to the second layer, wherein the first and second layers are separated by an insulating layer.

15. The method of claim 9, wherein the step of electroplating the first and second surfaces comprises the step of electroplating the first and second surfaces with a voltage source that produces a substantially square wave voltage output.

16. An integrated circuit, comprising:

a plurality of semiconductor devices formed on a semiconductor substrate;

a metallization layer formed outwardly from the semiconductor substrate that selectively interconnects the semiconductor devices so as to be operable to perform a function;

a first patterned layer of material formed outwardly from the semiconductor substrate that matches the metallization pattern; and

a second patterned layer of material, formed between the metallization layer and the first patterned layer, that matches the metallization pattern and lines contact vias that extend through the first layer to the semiconductor substrate.

17. The integrated circuit of claim 16, wherein the metallization layer comprises copper deposited on the second layer in an electrolytic bath.

18. The integrated circuit of claim 16, wherein the first layer comprises poly-silicon.

19. The integrated circuit of claim 16, wherein the second layer comprises titanium nitride.

20. The integrated circuit of claim 16, wherein the metallization layer comprises copper.

21. A semiconductor manufacturing system, comprising:

an electrolytic bath containing metal ions;

an anode; and

a modulating voltage supply to provide a bipolar modulated voltage between a substrate of a semiconductor device and the anode in the presence of the electrolytic bath, and wherein the modulated voltage has a first duty cycle and a second duty cycle,

wherein the metal ions are deposited on an exposed first layer of the semiconductor device and on a second layer of the semiconductor device during the first duty cycle, and

wherein the metal ions are removed from the exposed first layer during the second duty cycle.

22. The semiconductor manufacturing system of claim 21, wherein the first layer has a first surface voltage and the second layer has a second surface voltage, and the first surface voltage is lower than the second surface voltage.

23. The semiconductor manufacturing system of claim 21, further comprising a voltage supply circuit to supply a first potential to the exposed first layer and a second potential to the second layer.

24. The semiconductor manufacturing system of claim 23, wherein the voltage supply circuit includes a first voltage supply to supply a first potential to the exposed first layer, and a second voltage supply to supply a second potential to the second layer.

25. The semiconductor manufacturing system of claim 21, wherein the electrolytic bath contains copper ions to form a copper metallization layer.

26. The semiconductor manufacturing system of claim 21, wherein the electrolytic bath contains nickel ions to form a nickel metallization layer.

27. The semiconductor manufacturing system of claim 21, wherein the electrolytic bath contains palladium ions to form a palladium metallization layer.

28. A semiconductor manufacturing system for forming a metallization layer on a semiconductor device having a substrate, a first layer of material on the substrate, and a patterned second layer of material on the first layer of material, the system comprising:

an anode;

an electrolytic bath of metal ions for the semiconductor device; and

a modulating voltage supply to provide a bipolar modulating voltage between the anode and the substrate of the semiconductor device.

29. The semiconductor manufacturing system of claim 28, wherein the first material has a first potential and the second material has a second potential.

30. The semiconductor manufacturing system of claim 28, comprising a voltage supply circuit to provide a first potential to the first layer of material and a second potential to the second layer of material.

31. The semiconductor manufacturing system of claim 28, further comprising a DC offset voltage in series with the modulating voltage supply.

32. The semiconductor manufacturing system of claim 28, wherein the modulating voltage supply includes a square wave voltage supply.

33. The semiconductor manufacturing system of claim 28, wherein the modulating voltage supply includes a triangle wave voltage supply.

34. The semiconductor manufacturing system of claim 28, wherein the modulating voltage supply includes a sinusoidal wave voltage supply.

35. A semiconductor manufacturing system for forming a metallization layer on a semiconductor device having a substrate, a first layer of material on the substrate, and a patterned second layer of material on the first layer of material, the system comprising:

an anode;

a modulating voltage supply to provide a bipolar modulating voltage with a DC offset between the anode and the substrate of the semiconductor device; and

an electrolytic bath of copper ions for the semiconductor device.

36. The semiconductor manufacturing system of claim 35, wherein the first material has a first potential and the second material has a second potential.

37. The semiconductor manufacturing system of claim 35, further comprising a voltage supply circuit to provide a first potential to the first layer of material and a second potential to the second layer of material.

38. The semiconductor manufacturing system of claim 35, wherein the modulating voltage supply includes a square wave voltage supply.

39. The semiconductor manufacturing system of claim 35, wherein the modulating voltage supply includes a triangle wave voltage supply.

40. The semiconductor manufacturing system of claim 35, wherein the modulating voltage supply includes a sinusoidal wave voltage supply.

41. A semiconductor manufacturing system for forming a metallization layer on a semiconductor device having a substrate, a first layer of material on the substrate, an insulator layer on the first layer of material, a patterned second layer of material on the insulator layer, the system comprising:

an anode;

a modulating voltage supply to provide a bipolar modulating voltage between the anode and the substrate of the semiconductor device;

a circuit to provide a first potential on the first layer of material and a second potential on the second layer of material; and

an electrolytic bath of metal ions for the semiconductor device.

42. The semiconductor manufacturing system of claim 41, wherein the metal ions include copper ions.

43. The semiconductor manufacturing system of claim 41, wherein the metal ions include nickel ions.

44. The semiconductor manufacturing system of claim 41, wherein the metal ions include palladium ions.

45. The semiconductor manufacturing system of claim 41, wherein:

the bipolar modulating voltage has a first duty cycle and a second duty cycle; and

metal ions are deposited on the first layer of material and the second layer of material during the first duty cycle, and are removed from the first layer of material during the second duty cycle.

46. A semiconductor manufacturing system for forming a metallization layer on a semiconductor device having a substrate, a first layer of material on the substrate, and a patterned second layer of material on the first layer of material, the system comprising:

an anode;

a circuit to provide a first potential on the first layer of material and a second potential on the second layer of material;

an electrolytic bath of metal ions for the semiconductor device; and

a modulating voltage supply to provide a bipolar modulating voltage with a DC offset between the anode and the substrate of the semiconductor device, the bipolar modulating voltage having a first duty cycle and a second duty cycle, wherein metal ions are deposited on the first layer of material and the second layer of material during the first duty cycle, and are removed from the first layer of material during the second duty cycle.

47. The semiconductor manufacturing system of claim 46, wherein the metal ions include copper ions.

48. The semiconductor manufacturing system of claim 46, wherein the metal ions include nickel ions.

49. The semiconductor manufacturing system of claim 46, wherein the metal ions include palladium ions.

50. A semiconductor manufacturing system, comprising:

means for forming a first layer overlying a substrate;

means for forming contact vias through the first layer to the substrate;

means for forming a patterned second layer overlying the first layer and lining the contact vias; and

means for forming a metallization layer, including means for applying a bipolar modulated voltage between the substrate and an anode in the presence of an electrolytic bath.

51. The semiconductor manufacturing system of claim 50, wherein the means for forming a metallization layer includes means for filling the contact vias.

52. The semiconductor manufacturing system of claim 50, further comprising means for applying a first potential to the first layer and a second potential to the second layer.

53. The semiconductor manufacturing system of claim 50, wherein the means for applying a bipolar modulated voltage between the substrate and an anode in the presence of an electrolytic bath includes means for providing a DC offset potential.

54. A semiconductor manufacturing system, comprising:

means for providing a semiconductor device having;

a substrate;

a first layer overlying the substrate; and

a second layer overlying the first layer, wherein the device has an exposed first layer portion and an exposed second layer portion; and

means for providing a bipolar modulated voltage between the substrate and an anode in the presence of an electrolytic bath containing metal ions,

wherein the modulated voltage has a first duty cycle and a second duty cycle;

wherein the metal ions are deposited on the exposed first layer portion and the exposed second layer portion during the first duty cycle; and

wherein the metal ions are removed from the exposed first layer portion during the second duty cycle.

55. The semiconductor manufacturing system of claim 54, further comprising means for applying a first potential to the first layer and a second potential to the second layer.

56. The semiconductor manufacturing system of claim 54, wherein the means for providing a bipolar modulated voltage includes providing a DC offset potential.

57. The semiconductor manufacturing system of claim 54, wherein the metal ions include copper ions.

58. The semiconductor manufacturing system of claim 54, wherein the metal ions include nickel ions.

59. The semiconductor manufacturing system of claim 54, wherein the metal ions include palladium ions.