Fabrication method of semiconductor integrated circuit device

• US 20030032284A1
• Filed: 07/03/2002
• Published: 02/13/2003
• Est. Priority Date: 08/07/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Maekawa, Atsushi, Enomoto, Hiroyuki, Tago, Kazutami
• Granted Patent: US 6,787,446 B2
• Time in Patent Office: Days
• US Class Current: 438/687
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76832 Multiple layers

Abstract

The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, or the silicon carbide film or the organic insulating film exposed to the side walls of the interconnection grooves are side-etched. When a lamination film made of a silicon oxide film, an organic insulating film, a silicon oxide film, an organic insulating film and a silicon carbide film is dry-etched to form interconnection grooves over Cu interconnections, a mixed gas of SF₆ and NH₃ is used as an etching gas for the silicon carbide film to work side walls of the interconnection grooves perpendicularly and further suppress defects that a deposit or a reactant adheres to the surface of the Cu interconnections exposed to the bottom of the interconnection grooves.

Claims

1. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide as a main component over the conductive layer; and

(c) using a mixed gas of SF₆ and NH₃ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

2. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide as a main component over the conductive layer; and

(c) using mixed gas of a first etching gas comprising at least one selected from the group made of SF₆, HCl, HBr, Cl₂, Cl₃F and CF₄ and a second etching gas comprising at least one selected from the group made of NH₃, N₂H₄, and a mixed gas of N₂ and H₂ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

3. The process according to claim 2, further comprising the steps of, after the step (b) and before the step (c):

forming a second insulating film having a smaller dielectric constant than silicon oxide over the first insulating film; and

dry-etching a portion of the second insulating film, thereby making an opening wherein the surface of the first insulating layer is exposed to its bottom.

4. The process according to claim 3, wherein the second insulating film is a coating film containing an aromatic polymer as a main component.

5. The process according to claim 4, wherein a mixed gas obtained by adding H₂O, at such a slight level that does not substantially oxidize the surface of the first conductive layer, to the mixed gas of the first etching gas and the second etching gas is used to dry-etch a portion of each of the second insulating film and the first insulating film anisotropically.

6. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a first interconnection made of a conductive film containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide as a main component over the first interconnection;

(c) forming a second insulating film made of an organic insulating film having a smaller dielectric constant than silicon oxide over the first insulating film;

(d) using a gas containing nitrogen and hydrogen to dry-etch a portion of the second insulating film, thereby making a portion of the first insulating film exposed;

(e) using a mixed gas of a first etching gas comprising at least one selected from the group made of SF₆, HCl, HBr, Cl₂ and CF₄ and a second etching gas comprising at least one selected from the group made of NH₃, N₂H₄, and a mixed gas of N₂ and H₂ to dry-etch the first insulating film exposed in the step (d), thereby making an interconnection groove wherein the surface of the first interconnection is exposed to its bottom;

(f) forming a second conductive film containing copper as a main component over the second insulating film to embed the second conductive film inside the interconnection groove; and

(g) removing the second conductive film outside the interconnection groove by chemical mechanical polishing to form a second interconnection made of the second conductive film.

7. The process according to claim 6, wherein the organic insulating film is a coating film containing an aromatic polymer as a main component.

8. The process according to claim 6, which further comprising the step of repeating the same steps from the step (b) to the step (g) plural times after the step (g), to form, over the second interconnection, interconnections of plural layers made of conductive films containing copper as a main component.

9. The process according to claim 6, wherein the mixed gas of the first etching gas and the second etching gas is decomposed in a plasma atmosphere.

10. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon nitride as a main component over the conductive layer; and

(c) using a mixed gas of SF₆, HBr and N₂ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

11. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon nitride as a main component over the conductive layer; and

(c) using a mixed gas of SF₆, HBr and NH₃ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

12. The process according to claim 11, further comprising the steps of, after the step (b) and before the step (c):

forming a second insulating film containing a siloxane-based insulating film having a smaller dielectric constant than silicon oxide over the first insulating film; and

dry-etching a portion of the second insulating film, thereby making an opening wherein the surface of the first insulating layer is exposed to its bottom.

13. The process according to claim 11, wherein the second insulating film is an insulating film containing SiOF as a main component.

14. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a first interconnection made of a first conductive film containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon nitride as a main component over the first interconnection;

(c) forming a second insulating film including a siloxane-based insulating film having a smaller dielectric constant than silicon oxide over the first insulating film;

(d) using a mixed gas of a hydrofluorocarbon gas or fluorocarbon gas, an inert gas and oxygen to dry-etch a portion of the second insulating film, thereby making a portion of the first insulating film exposed;

(e) using a mixed gas of SF₆, HBr and N₂ or a mixed gas of SF₆, HBr and NH₃ to dry-etch the first insulating film exposed in the step (d), thereby making an interconnection groove wherein the surface of the first interconnection is exposed to its bottom;

(f) forming a second conductive film containing copper as a main component over the second insulating film to embed the second conductive film inside the interconnection groove; and

(g) removing the second conductive film outside the interconnection groove by chemical mechanical polishing to form a second interconnection made of the second conductive film inside the interconnection groove.

15. The process according to claim 14, wherein the second insulating film is an insulating film containing SiOF as a main component.

16. The process according to claim 14, further comprising the step of repeating the same steps from the step (b) to the step (g) plural times after the step (g) to form, over the second interconnection, interconnections of plural layers made of conductive films containing copper as a main component.

17. The process according to claim 14, wherein the mixed gas of SF₆, HBr and N₂ or the mixed gas of SF₆, HBr and NH₃ is decomposed in a plasma atmosphere.

18. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide or silicon carbonitride as a main component over the conductive layer; and

(c) using a mixed gas of CHF₃ and N₂ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

19. The process according to claim 18, wherein in the mixed gas, the flow ratio of CHF₃ to N₂ ranges from 1/0.1 to 200.

20. The process according to claim 19, wherein in the mixed gas, the flow ratio of CHF₃ to N₂ ranges from 1/0.2 to 20.

21. The process according to claim 20, wherein in the mixed gas, the flow ratio of CHF₃ to N₂ ranges from 1/0.5 to 10.

22. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide, silicon carbonitride or silicon carboxide as a main component over the conductive layer; and

(c) using a mixed gas of at least one of CHF₃ and CF₄, and N₂ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

23. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a first interconnection made of a first conductive film containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide or silicon carbonitride as a main component over the first interconnection;

(c) forming a first interlayer insulating film over the first insulating film and subsequently dry-etching a portion of the first interlayer insulating film to make a portion of the first insulating film exposed;

(d) using a first etching gas to dry-etch the first insulating film exposed in the step (c), to form a first interconnection groove wherein the surface of the first interconnection is exposed to its bottom;

(e) forming a second interconnection made of a conductive film containing copper as a main component inside the first interconnection groove;

(f) forming a second insulating film containing silicon carbide or silicon carbonitride as a main component over the second interconnection;

(g) forming a second interlayer insulating film over the second insulating film and subsequently dry-etching a portion of the second interlayer insulating film to make a portion of the second insulating film exposed;

(h) using a second etching gas to dry-etch the second insulating film exposed in the step (g), to form a second interconnection groove wherein the surface of the second interconnection is exposed to its bottom; and

(i) forming a third interconnection made of a conductive film containing copper as a main component inside the second interconnection groove,

wherein one of the first and second etching gases is a mixed gas of a third etching gas comprising at least one selected from the group made of SF₆, HCl, HBr, Cl₂, ClF₃ and CF₄ and a fourth etching gas comprising at least one selected from the group made of NH₃, N₂H₄, and a mixed gas of N₂ and H₂, and

wherein the other thereof is a mixed gas of at least one of CHF₃ and CF₄, and N₂.

24. The process according to claim 23, wherein the one of the first and second etching gases is a mixed gas of SF₆ and NH₃ and the other is a mixed gas of CHF₃ and N₂.

25. The process according to claim 23, wherein when the first interlayer insulating film is an organic insulating film having a smaller dielectric constant than silicon oxide, the first etching gas is a mixed gas of CHF₃ and N₂, and when the second interlayer insulating film is an insulating film containing a siloxane-based insulating material as a main component, the second etching gas is a mixed gas of SF₆ and NH₃.

26. The process according to claim 25, wherein the first insulating film is a coating film containing an aromatic polymer as a main component.

27. The process according to claim 25, wherein the first insulating film is an insulating film containing SiOF as a main component.

28. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide or silicon carbonitride as a main component over the conductive layer; and

(c) using a mixed gas of SF₆ and NH₃ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

29. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide, silicon carbonitride or silicon carboxide as a main component over the conductive layer; and

(c) using a mixed gas of a first etching gas comprising at least one selected from the group made of SF₆, HCl, HBr, Cl₂, ClF₃ and CF₄ and a second etching gas comprising at least one selected from the group made of NH₃, N₂H₄, and a mixed gas of N₂ and H₂ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

30. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon nitride as a main component over the conductive layer; and

(c) using a mixed gas of at least one of CHF₃ and CF₄, and N₂ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.