Method and system for manufacturing semiconductor devices

• US 20030033046A1
• Filed: 10/09/2002
• Published: 02/13/2003
• Est. Priority Date: 07/17/2001
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Matsumoto, Shunichi, Yoshitake, Yasuhiro, Miwa, Toshiharu
• Granted Patent: US 6,801,827 B2
• Time in Patent Office: Days
• US Class Current: 700/121
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70525 Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure
• CPC Class Codes: G03F 7/706 Aberration measurement
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring

Abstract

A system for manufacturing a semiconductor device which predicts a difference in registration error between a circuit pattern and an overlay mark from a pattern dimension, illumination conditions and the wave aberration of an exposure lens, feeds a correction value based on the predicted difference back to an exposure device and modifies an overlay inspection data control limit.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

reading a dimension of a circuit pattern in a first layer formation process;

reading a dimension of an overlay mark in said first layer formation process;

reading illumination conditions in an exposure device in said first layer formation process;

reading a wave aberration corresponding to said circuit pattern in the exposure device in said first layer formation process;

reading a wave aberration corresponding to said overlay mark in said first layer formation process;

calculating transfer images of said circuit pattern and said overlay mark in said first layer formation process;

reading a dimension of a circuit pattern in a second layer formation process;

reading a dimension of an overlay mark in said second layer formation process;

reading illumination conditions in an exposure device in said second layer formation process;

reading a wave aberration corresponding to said circuit pattern in the exposure device in said second layer formation process;

reading a wave aberration corresponding to said overlay mark in said second layer formation process;

calculating transfer images of said circuit pattern and said overlay mark in said second layer formation process;

calculating a registration error between the transfer image of the circuit pattern in said first layer formation process and the transfer image of the circuit pattern in said second layer formation process as well as a registration error between the transfer image of the overlay mark in said first layer formation process and the transfer image of the overlay mark in said second layer formation process;

finding a relationship between the registration error of the transfer image of said circuit pattern and the registration error of the transfer image of said overlay mark;

predicting an actual registration error of the circuit pattern from actually measured registration error of the overlay mark; and

feeding said actual registration error of the circuit pattern back to the exposure device of said second layer formation process as a correction value.

2. The method as set forth in claim 1, wherein said circuit pattern is a circuit pattern having the strictest specifications.

3. A method for manufacturing a semiconductor device comprising the steps of:

calculating a registration error between a transfer image of a first circuit pattern formed when a circuit pattern of a first layer formation process is transferred with use of a first exposure device and a transfer image of a second circuit pattern formed when a circuit pattern of a second layer formation process is transferred onto the transfer image of said first circuit pattern with use of a second exposure device;

calculating a registration error between a transfer image of a first overlay mark formed when an overlay mark of said first layer formation process is transferred with use of a first exposure device and a transfer image of a second overlay mark formed when an overlay mark of said second layer formation process is transferred with use of said second exposure device;

finding a relationship between said calculated registration error between the transfer images of said first and second circuit patterns and said calculated registration error between the transfer images of said first and second overlay marks;

measuring a registration error between an transfer image formed when said first overlay mark is transferred with use of said first exposure device and a transfer image formed when said second overlay mark is transferred with use of said second exposure device;

predicting a registration error between transfer images of the actual circuit patterns from said measured registration error with use of said found relationship between said calculated registration errors of said circuit patterns and overlay marks; and

finding a correction of the exposure device of said second layer formation process from said predicted registration error between the transfer images of the actual circuit patterns and feeding said correction back to the exposure device of said second layer formation process.

4. A method for manufacturing a semiconductor device, comprising the steps of:

calculating registration errors between transfer images of first and second overlay marks and circuit patterns when the first overlay mark and circuit pattern are transferred on a substrate with use of a first exposure device and when the second overlay marks and circuit patterns are transferred on the substrate with use of a second exposure device, the transfer images obtained by the second exposure device being transferred onto said substrate at an area where said first overlay mark and circuit pattern are transferred;

finding a relationship between said calculated registration error between the transfer images of the overlay marks and said calculated registration error between the transfer images of the circuit patterns;

measuring an actual registration error between the transfer images of the first and second overlay marks formed when said first overlay mark is actually transferred with use of the first exposure device and when said second overlay mark is actually transferred with use of the second exposure device;

predicting an actual registration error between the transfer images of the circuit patterns from data on said measured actual registration error with use of said found relationship between the registration errors of the circuit patterns and the registration errors of the overlay marks;

finding a correction of the exposure device in said second layer formation process from said predicted actual registration error between the transfer images of the circuit patterns;

correcting said second exposure device on the basis of said found correction; and

subjecting the second circuit pattern by said corrected second exposure device to light exposure on the first circuit pattern subjected to light exposure by said first exposure device.

5. The method as set forth in claim 4, wherein said registration error between the transfer images of the circuit patterns is calculated with use of information on a dimension of the first circuit pattern and on a dimension of the second circuit pattern to be formed on said first circuit pattern, information on illumination conditions of the first exposure device for light exposure of said first circuit pattern and on illumination conditions of the second exposure device for light exposure of said second circuit pattern, and information on a wave aberration of said first exposure device and on a wave aberration of said second exposure device.

6. A method for manufacturing a semiconductor device, comprising the steps of:

calculating a relationship between a registration error between transfer images of first and second circuit patterns and a registration error between transfer images of first and second overlay marks with use of information on a dimension of said first circuit pattern and a dimension of said second circuit pattern to be formed on said first circuit pattern, information on illumination conditions of the first exposure device for light exposure of said first circuit pattern and on illumination conditions of the second exposure device for light exposure of said second circuit pattern, and information on a wave aberration of said first exposure device and on a wave aberration of said second exposure device;

measuring an actual registration error between a transfer image formed when said first overlay mark is actually transferred with use of said first exposure device and a transfer image formed when said second overlay mark is actually transferred with use of said second exposure device;

predicting an actual registration error between the transfer images of the circuit patterns from data about said actual registration error between the transfer images of the overlay marks with use of said calculated relationship between the registration errors between the transfer images of the circuit patterns and overlay marks;

correcting said exposure device of a second layer formation process on the basis of a correction corresponding to said predicted actual registration error between the transfer images of the circuit patterns; and

subjecting said second circuit pattern by said corrected second exposure device to light exposure on said first circuit pattern subjected by said first exposure device to light exposure.

7. The method as set forth in claim 6, wherein, in said step of correcting the exposure device of said second layer formation process, the exposure device of said second layer formation process is corrected by feeding a correction corresponding to said predicted actual registration error between the transfer images of the circuit patterns back to the exposure device of said second layer formation process.

8. The method as set forth in claim 6, wherein, in said step of correcting the exposure device of said second layer formation process, the exposure device of said first layer formation process is corrected on the basis of a correction corresponding to said predicted actual registration error between the transfer images of the circuit patterns.

9. A method for manufacturing a semiconductor device, comprising the steps of:

measuring an actual registration error between a transfer image formed when a first overlay mark formed on a first reticle is actually transferred on a substrate with use of a first exposure device and a transfer image formed when a second overlay mark formed on a second reticle is actually transferred on said substrate with use of a second exposure device;

predicting an actual registration error between the transfer images of the actual circuit patterns from data on said measured registration error between the transfer images of the overlay marks with use of a relationship between a transfer image formed when a first circuit pattern formed on said first reticle is transferred on said substrate with use of said first exposure device and a transfer image formed when a second circuit pattern formed on said second reticle is transferred on the substrate with use of said second exposure device and said registration error between the transfer images of the overlay marks;

correcting said second exposure device on the basis of information on said predicted actual registration error between the transfer images of the circuit patterns; and

subjecting said second circuit pattern by said corrected second exposure device to light exposure on said first circuit pattern subjected by said first exposure device to light exposure.

10. The method as set forth in claim 9, wherein, in said step of correcting said second exposure device, said second exposure device is corrected by feeding a correction corresponding to said predicted actual registration error between the transfer images of the circuit patterns back to said second exposure device.

11. The method as set forth in claim 9, wherein, in said step of correcting said second exposure device, said first exposure device is also corrected on the basis of a correction corresponding to said predicted actual registration error between the transfer images of the circuit patterns.

12. A system for manufacturing a semiconductor device, comprising:

history storage means for storing a history of an exposure device, illumination conditions and a reticle used for manufacturing of a substrate to be exposed;

reticle data storage means for storing a dimension of a circuit pattern of the reticle, a dimension of an overlay mark, a coordinate value of said circuit pattern and a coordinate value of said overlay mark;

illumination conditions storage means for storing the exposure device and illumination conditions for each process;

wave aberration data storage means for storing wave aberration data for each exposure device and each pattern coordinate value;

registration error calculation means for calculating a circuit pattern registration error of a second layer formation process to a first layer formation process and an overlay mark registration error of said second layer formation process to said first layer formation process from said illumination conditions, said circuit pattern dimension, said overlay mark dimension and said wave aberration for each coordinate value;

registration error relationship calculation means for calculating a relationship between said circuit pattern registration error and said overlay mark registration error;

registration error relationship storage means for storing said registration error relationship, a name of said first layer formation process, a name of said second layer formation process, exposure devices, illumination conditions and reticles used in said first and second layer formation processes;

overlay control limit storage means for storing an overlay control limit for each product and process;

overlay control limit conversion means for converting said overlay control limit from said registration error relationship;

overlay inspection data storage means for storing overlay inspection data;

correction calculating means for calculating a correction of said second exposure device from said registration error relationship and said overlay inspection data;

a host computer for performing control of an entire semiconductor manufacturing apparatus and input and output of information;

input/output control means for performing transfer of information of said plurality of storage means, a plurality of calculation means, selection means and judgement means and transmitting a correction value calculated by a start device issued from said start device judging means and by said correction value calculation means or a correction value issued from a combination of said information storage means to said host computer;

an exposure device; and

an overlay inspection device.

13. A system for manufacturing a semiconductor device, comprising:

a first exposure device for subjecting a circuit pattern formed on a first reticle and an overlay mark to light exposure and transfer on a substrate;

a second exposure device for subjecting a circuit pattern formed on a second reticle and an overlay mark to light exposure and transfer as overlapped with said circuit pattern formed on said first reticle and said circuit pattern subjected to light exposure and transfer on said substrate;

an overlay inspection device for measuring a registration error between a transfer image of a first overlay mark subjected by said first exposure device to light exposure and transfer and a transfer image of a second overlay mark by said second exposure device to light exposure and transfer;

registration error calculation means for calculating registration errors between a transfer image of a first circuit pattern formed when the circuit pattern formed on said first reticle and overlay mark are transferred on the substrate with use of said first exposure device, a transfer image of a second circuit pattern formed when the circuit pattern formed on said second reticle and overlay mark are transferred with use of said second exposure device as overlapped with said first overlay mark, a transfer image of said first circuit pattern of a transfer image of said second overlay mark, and a transfer image of said first overlay mark;

registration error relationship calculation means for finding a relationship between a registration error of the transfer image of the circuit pattern and a registration error of the transfer image of the overlay mark from a relationship between a registration error between the transfer image of said first circuit pattern found by said registration error calculation means and the transfer image of said second circuit pattern and a registration error between the transfer image of said first overlay mark and the transfer image of said second overlay mark;

correction calculating means for calculating a correction of said second exposure device by predicting an actual registration error between the transfer images of the circuit patterns with use of said relationship found by said registration error relation calculating means on the basis of data on said registration error measured by said overlay inspection device; and

output means for outputting information on said correction of said second exposure device calculated by said correction calculating means.

14. The system as set forth in claim 13, further comprising correction means for correcting said second exposure device on the basis of said correction information of said second exposure device outputted from said output means.