Method and apparatus for software-based allocation and scheduling of hardware resources in an electronic device

• US 20030033411A1
• Filed: 08/09/2001
• Published: 02/13/2003
• Est. Priority Date: 08/09/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Holmes, David M., Rieken, Keith, Kavoori, Chakki
• Granted Patent: US 7,536,691 B2
• Time in Patent Office: Days
• US Class Current: 709/226
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04W 72/1215 for collaboration of different radio technologies
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

An architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware resources in a communication device having a processor, a computer readable memory, and at least one hardware resource coupled to each other includes several steps. The first step locates a memory address in the computer readable memory that is associated with a first hardware resource. In the next step, control information associated with the first memory address is transmitted to the first hardware resource for it to be operated. In the last step, a pointer associated with the first address that locates a subsequent address for a subsequent hardware resource, is read.

Claims

1. In an electronic device having a processor, a computer readable memory, and at least one hardware resource coupled to each other, a method of OPERATING the hardware resources, the method comprising the steps of:

a) locating a first address in the computer readable memory, the first address containing operating information associated with a first hardware resource;

b) transmitting operating information associated with the first address to the first hardware resource;

c) reading a pointer associated with the first address that locates a subsequent address for a subsequent hardware resource; and

d) repeating steps a) through c) for a quantity of pointers respectively associated with multiple hardware resources.

2. The electronic device recited in claim 1 wherein the method further comprises the step of:

e) returning to the first pointer when all of the quantity of pointers has been exhausted in a list stored in memory.

3. The electronic device recited in claim 1 wherein the method further comprises the step of:

e) repeating steps a) through c) for each of multiple sets of operating information associated with multiple uses of the hardware resource.

4. The electronic device recited in claim 3 wherein the multiple sets of operating information are utilized within a system cycle.

5. The electronic device recited in claim 1 wherein the method further comprises the step of:

e) repeating steps a) through d) for a plurality of entries of operating information for the hardware resource, wherein each of the entries is respectively associated with a reuse of the hardware resource for a different application at a different point in time.

6. The electronic device recited in claim 1 wherein the information for operating the first hardware resource includes semi-static hardware control parameters.

7. The electronic device recited in claim 6 wherein the semi-static hardware control parameters include flags, parameters, or states for the first hardware resource.

8. The electronic device recited in claim 1 wherein the information for operating the first hardware resource includes dynamic hardware control parameters.

10. The electronic device recited in claim 8 wherein the dynamic hardware parameters are controlled by dedicated hardware resources.

11. The electronic device recited in claim 7 wherein the hardware resources include at least one tracking finger.

12. The electronic device recited in claim 1 wherein the hardware resources include at least one searcher element.

13. The electronic device recited in claim 1 wherein the hardware resources include at least one downlink transmitter element.

14. The electronic device recited in claim 1 wherein the hardware resources include at least one matched filter element.

16. The electronic device recited in claim 1 wherein only the hardware resources in the secondary list that are grouped together for a specific category are enabled via the pointer from the primary list.

17. The electronic device recited in claim 16 wherein the secondary list has a pointer at the end of the operating information grouped together for the specific purpose, the pointer for the secondary list returning control to the primary list.

18. The electronic device recited in claim 16 wherein the primary list has a plurality of pointers that point to at least one other list that tracks an identification of a user of hardware resources.

15. The electronic device recited in claim 15 wherein the method further comprises the step of:

e) executing a pointer from a primary list of pointers that transfers control to a secondary list with operating information associated with the hardware resource.

19. In an electronic device having a processor, a computer readable memory, and at least one hardware resource all coupled to each other, a method of generating a scheduler for managing the hardware resource, the method comprising the steps of:

a) receiving at the electronic device, a quantity of hardware resources available in the electronic device;

b) receiving operation information for the hardware resource; and

c) generating a list in memory for linking requests for using the hardware resource.

20. The electronic device recited in claim 19 wherein the method further comprises the steps of:

d) receiving a request from a requester for using the hardware resource in the electronic device; and

e) associating operating information for the given hardware resource with the requester in an entry of the list.

21. The electronic device recited in claim 19 wherein the hardware resources managed by the list have the same function.

22. The electronic device recited in claim 19 further comprising the step of:

d) generating a memory address that links the operation information of the hardware resources to another hardware resource.

23. The electronic device recited in claim 20 further comprising the step of:

f) generating a memory address that links a last hardware resource to a first hardware resource.

24. The electronic device recited in claim 20 further comprising the step of:

f) generating a memory address that links the hardware resources for each of multiple reuses within the given time span.

25. The electronic device recited in claim 20 further comprising the step of:

f) generating a second list that provides a pointer to operation information of hardware resources that have a common category.

26. A system for communicating information between a host communication device and an external communication device, the system comprising:

receiving a request for using a hardware resource in the host communication device for communicating to the external communication device;

modifying a scheduler for the hardware resources in computer memory of the host communication device to satisfy the request; and

operating the hardware resources in the host communication device according to the modified scheduler.

27. In an electronic device having a processor, a means for storing a list of information, and at least one hardware resource coupled to each other, a method of operating the hardware resources, the method comprising the steps of:

a) locating a first address in the means for storing a list of information, the first address containing operating information associated with a first hardware resource;

b) transmitting operating information associated with the first address to the first hardware resource;

c) reading a pointer associated with the first address that locates a subsequent address for a subsequent hardware resource; and

d) repeating steps a) through c) for a quantity of pointers respectively associated with multiple hardware resources.