Mems devices suitable for integration with chip having integrated silicon and compound semiconductor devices, and methods for fabricating such devices

• US 20030034535A1
• Filed: 08/15/2001
• Published: 02/20/2003
• Est. Priority Date: 08/15/2001
• Status: Abandoned Application

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Cornett, Kenneth D., Barenburg, Barbara Foley, Gorrell, Jonathan F.
• Application Number:
  US09/929,020
• Publication Number:
  US 20030034535A1
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H03H 3/0073 Integration with other electronic structures
• CPC Class Codes: H03H 9/2463 Clamped-clamped beam resonators
• CPC Class Codes: H10N 30/079 using intermediate layers, e.g. for growth control
• CPC Class Codes: H10N 30/2042 Cantilevers, i.e. having one fixed end
• CPC Class Codes: H10N 30/708 Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
• CPC Class Codes: H10N 30/8542 Alkali metal based oxides, e.g. lithium, sodium or potassium niobates
• CPC Class Codes: H10N 39/00 Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00

Abstract

High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Claims

1. A microelectromechanical device comprising:

a monocrystalline substrate;

a piezoelectric material selected from the group consisting of alkaline earth titanates, zirconates, hafnates, niobates, tantalates, and the tin-based perovskites overlying the monocrystalline substrate; and

one or more electrodes proximate the piezoelectric material for applying one or more piezoelectric action inducing electric fields to the perovskite material.

2. The microelectromechanical device according to claim 1 wherein the monocrystalline substrate comprises:

a diamond lattice crystal of a material selected from the group consisting of silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, and germanium and carbon.

3. The microelectromechanical device according to claim 2 further comprising:

an amorphous oxide material that is interposed between the monocrystalline substrate and the piezoelectric material and is in direct contact with the monocrystalline substrate and the piezoelectric material.

4. The microelectromechanical device according to claim 2 wherein the monocrystalline substrate comprises:

a monocrystalline silicon.

5. The microelectromechanical device according to claim 1 further comprising:

a semiconductor material layer overlying the piezoelectric material.

6. The microelectromechanical device according to claim 5 wherein:

the perovskite material includes;

one or more edge walls bounding a gap in the piezoelectric material;

the semiconductor material layer includes;

a bridge including;

a first end overlying the piezoelectric material;

a second end overlying the piezoelectric material; and

a middle portion extending across the gap; and

the one or more electrodes include;

a first electrode overlying the first end of the bridge.

7. The microelectromechanical device according to claim 6 wherein the one or more electrodes further comprise:

a second electrode overlying the second end of the bridge.

8. The microelectromechanical device according to claim 6 wherein:

the semiconductor material layer comprises a compound semiconductor.

9. The microelectromechanical device according to claim 5 wherein:

the piezoelectric material comprises;

a first pedestal formed out of the piezoelectric material;

a second pedestal formed out of the piezoelectric material;

a third pedestal that is located between the first pedestal, and the second pedestal and is formed out of the piezoelectric material; and

a fourth pedestal that is located between the second pedestal and the third pedestal and is formed out of the piezoelectric material;

the semiconductor material layer comprises;

a bridge of semiconductor material spanning between the first pedestal and second pedestal, and over the third pedestal and the fourth pedestal; and

the one or more electrodes comprises;

a first electrode located on the bridge over the first pedestal;

a second electrode located on the bridge over the second pedestal;

a third electrode located on the bridge over the third pedestal; and

a fourth electrode located on the bridge over the fourth pedestal.

10. The microelectromechanical device according to claim 9 wherein the semiconductor material layer further comprises:

a multilayer interference film.

11. The microelectromechanical device according to claim 9 further comprising:

a mirror supported on the bridge of semiconductor material between the second pedestal and the third pedestal.

12. The microelectromechanical device according to claim 1 wherein:

the piezoelectric material includes;

an upper surface;

a lower surface; and

a first cantilevered beam shaped portion including;

a clamped end that is supported on the monocrystalline substrate; and

a free end.

13. The microelectromechanical device according to claim 12 wherein:

the one or more electrodes include;

a first electrode located proximate the clamped end; and

a second electrode located proximate the free end.

14. The microelectromechanical device according to claim 13 wherein:

the first cantilevered beam shaped portion is polarized in a direction approximately parallel to a longitudinal axis of the cantilevered beam shaped portion.

15. The micromechanical device according to claim 13 further comprising:

a conductor extending from the clamped end to the second electrode.

16. The microelectromechanical device according to claim 12 wherein:

the monocrystalline substrate comprises one or more edges defining an opening through the monocrystalline layer aligned with the first cantilevered beam shaped portion.

17. The microelectromechanical device according to claim 16 further comprising:

a cantilevered beam shaped portion of semiconductor material overlying the first cantilevered beam shaped portion proximate the upper surface.

18. The microelectromechanical device according to claim 17 wherein the one or more electrodes comprise:

an electrode adjacent to the second surface.

19. The microelectromechanical device according to claim 18 further comprising:

a via that extends through the monocrystalline substrate and is electrically coupled to the electrode adjacent to the second surface.

20. The microelectromechanical device according to claim 1 further comprising:

an optical component mechanically coupled to the piezoelectric material.

21. The microelectromechanical device according to claim 20 wherein:

the optical component comprises a reflector.

22. The microelectromechanical device according to claim 20 wherein:

optical component comprise comprises a multilayer interference film formed on piezoelectric material.

23. The microelectromechanical device according to claim 22 wherein:

the multilayer interference film comprises a plurality of layers of III-V type semiconductor.

24. The microelectromechanical device according to claim 22 wherein:

the piezoelectric material comprises one or more edges bounding a gap in the piezoelectric material underlying the first multilayer interference film.

25. The microelectromechanical device according to claim 1 wherein the one or more electrodes comprise:

a first electrode including a first plurality of fingers; and

a second electrode including a second plurality of fingers that are interdigitated with the first plurality of fingers.

26. The microelectromechanical device according to claim 25 further comprising:

a third electrode that includes a third plurality of fingers and is located in spaced relation to the first electrode and the second electrode on the piezoelectric material; and

a fourth electrode including a fourth plurality of fingers that are interdigitatated with the third plurality of fingers.

27. A method of fabricating a piezoelectric device, the method comprising the steps of:

obtaining a diamond lattice monocrystalline substrate;

growing a piezoelectric layer including a material selected from the group consisting of alkaline earth titanates, zirconates, hafnates, niobates, tantalates, and the tin-based perovskites over the monocrystalline substrate;

etching the piezoelectric layer to define a piezoelectric transducer;

forming one or more electrodes proximate the piezoelectric transducer; and

polarizing the piezoelectric transducer.

28. The method of claim 27 wherein the step of growing a piezoelectric layer comprises the sub-step of:

growing a piezoelectric layer that is substantially lattice matched to the diamond lattice monocrystalline substrate over the monocrystalline substrate.

29. The method according to claim 27 wherein the step of growing the piezoelectric layer includes the step of:

concurrently growing an amorphous interface layer between the diamond lattice monocrystalline substrate and the piezoelectric layer.

30. The method according to claim 27 further comprising the step of:

forming a crystalline template layer that chemically bonds to the piezoelectric layer on the piezoelectric layer; and

forming a semiconductor material layer that chemically bonds to the crystalline template layer on the template layer.

31. The method according to claim 30 further comprising the step of:

etching the semiconductor material layer to define one or more semiconductor material parts of the piezoelectric device.

32. The method according to claim 31 wherein the step of etching the semiconductor material layer comprises the step of:

etching the semiconductor material layer to define a beam including a first, second end, and a midsection.

33. The method according to claim 32 further comprising the step of:

etching a portion of the piezoelectric layer out from under the midsection of the beam, whereby a beam that is suspended at at least two ends on the piezoelectric layer is obtained.

34. The method according to claim 33 wherein the step of forming one or more electrodes comprises the sub-step of:

forming a first electrical contact proximate the first end of the beam.

35. The method according to claim 34 wherein the step of forming one or more electrodes further comprises the sub-step of:

forming a second electrical contact proximate the second end of the beam.

36. The method according to claim 35 further comprising the step of:

forming a mirror on the midsection of the beam.

37. The method according to claim 36 wherein the step of forming a mirror comprises the sub-step of:

depositing a stack of monocrystalline material layers characterized by a plurality of refractive indexes on the midsection of the beam.

38. The method according to claim 27 wherein the step of forming one or more electrodes comprises the sub-steps of:

depositing a monocrystalline semiconductor layer on the piezoelectric layer; and

doping the monocrystalline semiconductor layer.

39. The method according to claim 38 wherein the step of doping the monocrystalline layer comprises the sub-step of:

doping the monocrystalline semiconductor layer to define a first electrode that includes a first plurality of fingers, and a second electrode that includes a second plurality of fingers that are interdigitated with the first plurality of fingers.

40. The method according to claim 27 further comprising the step of:

etching an opening through the monocrystalline substrate up to the piezoelectric layer.

41. The method according to claim 40 wherein the step of etching the piezoelectric perovskite layer comprises the sub-step of:

etching the piezolelectric layer over the opening to define a cantilevered beam.

42. The method according to claim 41 further wherein the step of forming one or more electrodes comprises the sub-step of:

depositing a lower electrode through the opening onto the piezoelectric layer

43. The method according to claim 41 further comprising the step of:

forming a via through the monocrystalline substrate to the lower electrode.

44. The method according to claim 41 further comprising the steps of:

depositing a semiconductor material layer over the piezoelectric layer; and

etching the semiconductor material layer to form an upper layer of the cantilevered beam.

45. The method according to claim 44 wherein the step of forming one or more electrodes comprises the sub-step of:

forming one or more electrical contacts on the upper layer of the cantilevered beam.