Memory circuit
First Claim
Patent Images
1. A memory device comprising:
- a substrate extending in a plane;
an array of memory elements arranged in a plurality of rows and a plurality of columns arranged substantially parallel to the plane of the substrate and over a predetermined area of the substrate;
a plurality of row conductors extending along the rows of memory elements and connecting to the memory elements of the respective rows;
a plurality of column conductors extending along the columns of memory elements and connecting to the memory elements of the respective columns;
a plurality of driver cells containing drivers for driving the row and/or column conductors, arranged in a layer between the memory array and the substrate, and an insulating layer between the driver cells and the array of memory cells, a plurality of conductors passing through the insulating layer distributed over the predetermined area connecting the driver cells to corresponding row or column conductors.
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Abstract
A memory device comprises an array of memory elements (15) overlying driver cells (3). Vias (21) connect the driver cells (3) to the memory elements (15). The vias are distributed over the area of the array to connect the driver cells (3) to the row and column conductors (9, 13) of the memory array.
1 Citation
10 Claims
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1. A memory device comprising:
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a substrate extending in a plane;
an array of memory elements arranged in a plurality of rows and a plurality of columns arranged substantially parallel to the plane of the substrate and over a predetermined area of the substrate;
a plurality of row conductors extending along the rows of memory elements and connecting to the memory elements of the respective rows;
a plurality of column conductors extending along the columns of memory elements and connecting to the memory elements of the respective columns;
a plurality of driver cells containing drivers for driving the row and/or column conductors, arranged in a layer between the memory array and the substrate, and an insulating layer between the driver cells and the array of memory cells, a plurality of conductors passing through the insulating layer distributed over the predetermined area connecting the driver cells to corresponding row or column conductors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of manufacturing a memory device on a substrate extending in a plane, including
defining an array of driver cells including at least column drivers over the substrate; -
depositing an insulating layer over the array of driver cells;
depositing a plurality of column conductors over the insulating layer;
defining an array of memory elements arranged in a plurality of rows and a plurality of columns substantially over the array of driver cells; and
depositing a plurality of row conductors.
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Specification