Circuit for testing an integrated circuit

• US 20030035400A1
• Filed: 07/30/2002
• Published: 02/20/2003
• Est. Priority Date: 07/31/2001
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Infineon Technologies AG
• Inventors: Berger, Hartmut, Adler, Frank
• Granted Patent: US 6,781,398 B2
• Time in Patent Office: Days
• US Class Current: 370/338
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A test circuit for testing an integrated circuit, includes a test signal input for receiving a test signal from the integrated circuit and a reference signal input for receiving a reference signal. A comparator is in communication with the test signal input and with the reference signal input. The comparator is configured to provide, at a comparator output, an error signal if a comparison between the reference signal and the test signal indicates an error. The error signal, if present, is stored in an error memory, in communication with the comparator output.

Claims

1. A test circuit for testing an integrated circuit, the test circuit comprising:

a test signal input for receiving a test signal from the integrated circuit;

a reference signal input for receiving a reference signal;

a comparator in communication with the test signal input and with the reference signal input, the comparator being configured to provide, at a comparator output, an error signal if a comparison between the reference signal and the test signal indicates an error;

an error memory, in communication with the comparator output, for storing the error signal; and

an error signal output in communication with the error memory.

2. The test circuit of claim 1, wherein the comparator is configured to output a binary error signal in response to a comparison of voltages of the test signal and the reference signal.

3. The test circuit of claim 1, wherein the error memory comprises a flip-flop.

4. The test circuit of claim 1, further comprising a reset signal input connected to the error memory for erasing an error state thereof.

5. The test circuit of claim 1, wherein

the comparator is configured to output a first error signal when a test signal voltage of the test signal exceeds a reference signal voltage of a reference signal,

and the circuit further comprises:

an additional reference signal input for receiving an additional reference signal, and

an additional comparator in communication with the test signal input and with the additional reference signal input, the additional comparator being configured to provide, at an additional comparator output, an additional error signal when a reference signal voltage of the additional reference signal exceeds the test signal voltage.

6. The test circuit of claim 5, further comprising an additional error memory in communication with the additional comparator output for storing the additional error signal, the additional error memory being in communication with the error signal output.

7. The test circuit of claim 6, wherein the error memory and the additional error memory are configured to be read separately from each other at the error signal output.

8. A system for testing an integrated circuit, the system comprising:

a test circuit as recited in claim 1,

a programmable driver output for outputting the reference signal to the reference signal input of the test circuit, and

a test result input in communication with the error signal output for receiving the error signal.

9. The system of claim 8, wherein the test circuit comprises an ASIC (“

application specific integrated circuit”

).

10. The system of claim 8, wherein the test circuit comprises a programmable logic array.

11. The system of claim 8, wherein the programmable driver output comprises an analog high-speed output.

12. The system of claim 11, wherein the test result input is a low speed input.

13. A system for testing an integrated circuit, the system comprising:

a test circuit as recited in claim 5,

a first programmable driver output for outputting the reference signal to the reference signal input of the test circuit,

a second programmable driver output for outputting the additional reference signal to the additional reference signal input, and

a test result input in communication with the error signal output for receiving the error signal.

14. The system of claim 8, further comprising an additional programmable driver output in communication with the test signal input.

15. The system of claim 14, wherein the additional programmable driver output forms an active termination of the test signal input.

16. A method of testing a test signal of a DDR-DIMM, the method comprising:

providing a system as recited in claim 8, and

providing the test signal to the system.

17. A method of testing a test signal generated by an integrated circuit, the method comprising:

providing the test signal to a test signal input of a test circuit;

providing a reference signal into a reference signal input of the test circuit;

comparing the test signal and reference signal with a comparator;

storing an error signal into an error memory when the comparison of the test signal and the reference signal indicates an error; and

reading the error signal from the error memory.

18. The method of claim 17, wherein comparing the test signal comprises providing an external control signal to the comparator for causing the comparator to enter a comparison mode.