System and method for providing slicer level adaption

• US 20030035497A1
• Filed: 08/16/2002
• Published: 02/20/2003
• Est. Priority Date: 08/17/2001
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Gorecki, James, Yang, Yaohua, Martin, David A.
• Granted Patent: US 7,248,640 B2
• Time in Patent Office: Days
• US Class Current: 375/317
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 27/08 Amplitude regulation arrangements

Abstract

The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs an automatic slicer level adaption to enhance the performance of a high speed communications system.

Claims

1. A reference generator circuit for a receiver module coupled to a digital communications channel, the reference generator circuit comprising:

a reference voltage generation module to generate an adjustable reference voltage within the receiver module;

an error measurement module, coupled to the reference voltage generation module, to determine an error signal value between a measured received signal and a desired signal; and

wherein the reference voltage generation module uses the error signal to control the magnitude of the adjustable reference voltage.

2. The reference generator circuit according to claim 1, wherein a range of voltage values corresponding to a received symbol are decoded as a particular symbol using a maximum reference voltage and minimum reference voltage;

and

the maximum reference voltage and minimum reference voltage are adjusted using error statistics collected within the error measurement module using the incoming data stream.

3. The reference generator circuit according to claim 2, wherein adaption of the maximum reference voltage and minimum reference voltage is performed during an initialization process.

4. The reference generator circuit according to claim 2, wherein the statistics within the error measurement module are collected using the equation:

μ

_asl×

sgn[Σ

sgn(e(n))·

sgn(d(n))], for n=1 to N where N≧

64, or 128, or 255.

5. The reference generator circuit according to claim 2, wherein adaption of the maximum reference voltage and minimum reference voltage is performed continuously, periodically, or intermittently.

6. The reference generator circuit according to claim 5, wherein the adaption of the maximum reference voltage and minimum reference voltage is selectively enabled or disabled.

7. The reference generator circuit according to claim 5, wherein the maximum reference voltage and minimum reference voltage reference magnitude are externally set to a predetermined value.

8. A reference generator circuit according to claim 5, where the spacing between reference levels is non-uniform.

9. The reference generator circuit according to claim 8, wherein a performance criteria for setting the non-uniformity between the range of voltage values is a measure of a bit-error rate (BER) for the receiver module.

10. The reference generator circuit according to claim 1, wherein the spacing between reference levels is non-uniform.

11. The reference generator according to claim 10, wherein the nonuniformity is asymmetric.