Method and apparatus for skip-free retiming transmission of digital information

• US 20030035504A1
• Filed: 08/19/2002
• Published: 02/20/2003
• Est. Priority Date: 08/17/2001
• Status: Active Grant

• Current Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Original Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Inventors: Wong, Brian, Tang, Benjamim, Southwell, Scott, Sakai, Allen
• Granted Patent: US 7,194,059 B2
• Time in Patent Office: Days
• US Class Current: 375/377
• CPC Class Codes: H04L 25/242 with retiming

Abstract

A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.

Claims

1. A skip-free data communication system comprising:

a first node configured to transmit a data stream at a first rate;

a second node configured to transmit a data stream at a second rate; and

a plurality of retimers in serial data path between said first and second nodes, said retimers configured to receive said data stream at said first rate and retime said data stream by rate compensating a local clock of said retimer to match said first rate, said retimers configured to transmit a retimed data stream at a rate of said first rate,

wherein said retimed data stream being received at said second node at said first rate regardless of the number of said retimers between said first and second nodes.

2. The data communication system of claim 1, wherein said retimers configured to receive said Fc2 data stream and retime said Fc2 data stream by rate compensating said local clock of said retimer to match said Fc2 data stream and to transmit a retimed data stream at a rate of Fc2 to said first node.

3. The data communication system of claim 1, wherein said retimers configured to reset a jitter budget and amplify said received data stream.

4. The data communication system of claim 1, wherein said plurality of retimers comprises an unlimited number.

5. The data communication system of claim 1, wherein said system comprises a plesiochronous system.

6. The data communication system of claim 1, wherein said first and second nodes comprise a digital subsystem and a frequency compensation system.

7. The data communication system of claim 1, wherein said retimers comprise:

a clock and data recovery block configured to receive said data stream at said first rate, to recover a clock frequency from said received data stream, and to reclock said data stream;

a memory device configured to receive and store said reclocked data stream;

a frequency multiplier configured to generate said local clock;

a phase comparator configured to determine a frequency offset between said local clock and said recovered clock; and

a frequency shifter configured to generate a clean data clock corresponding to said frequency offset, said clean data clock being received at said memory device, wherein said retimed data stream being transmitted from said memory device at said first rate.

8. The data communication system of claim 7, wherein said memory device comprises a first-in first-out (FIFO) device.

9. The data communication system of claim 7, wherein said local clock being within a limited frequency offset of said first rate.

10. The data communication system of claim 7, further comprising a filter configured to receive said frequency offset and filter a jitter from said recovered clock.

11. A retimer for use in a digital data communications system, said retimer comprising:

a clock and data recovery block configured to receive a data stream at a first rate, to recover a clock frequency from said received data stream, and to reclock said data stream;

a memory device configured to receive and store a reclocked data stream;

a frequency multiplier configured to generate a local clock;

a phase comparator configured to determine a frequency offset between said local clock and said recovered clock; and

a frequency shifter configured to generate a clean data clock corresponding to said frequency offset, said clean data clock being received at said memory device, wherein a retimed data stream being transmitted from said memory device at said first rate.

12. The data communication system of claim 11, wherein said memory device comprises a first-in first-out (FIFO) device.

13. The data communication system of claim 11, wherein said local clock being within a limited frequency offset of said first rate.

14. The data communication system of claim 11, further comprising a filter configured to receive said frequency offset and filter a jitter from said recovered clock.

15. A method of skip-free retiming in a plesiochronous data communication system, said method comprising:

receiving a data stream at a first frequency;

recovering a clock from said data stream, said recovered clock including said first frequency and a jitter;

generating a reference clock free from jitter and having a second frequency;

comparing said recovered clock and said reference clock to determine a frequency offset;

phase shifting said reference clock according to said frequency offset; and

transmitting a retimed data stream at said first frequency and corresponding to said phase shifted clock.

16. The method of skip-free retiming of claim 15, further comprising filtering said frequency offset to remove said jitter.

17. The method of skip-free retiming of claim 15, further comprising receiving said data stream at a clock and data recovery (CDR) circuit.

18. The method of skip-free retiming of claim 17, further comprising reclocking said data stream at said first frequency at said CDR circuit.

19. The method of skip-free retiming of claim 15, further comprising storing said reclocked data stream in a FIFO (first-in first-out).

20. The method of skip-free retiming of claim 15, further comprising:

transmitting said data stream at said first frequency from a first node;

receiving said data stream at said first frequency at a plurality of retimers and retiming said data stream according to claim 8 such that each of said retimers transmits a retimed data stream at said first frequency; and

receiving said data stream at said first frequency from said plurality of retimers at an end node.