Low dielectric constant etch stop films

• US 20030036280A1
• Filed: 07/09/2002
• Published: 02/20/2003
• Est. Priority Date: 04/05/2000
• Status: Abandoned Application

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Jain, Sanjeev, MacWilliams, Kenneth P., Kooi, Gerrit, Nag, Somnath, Karim, M. Ziaul
• Application Number:
  US10/192,825
• Publication Number:
  US 20030036280A1
• Time in Patent Office: Days
• US Class Current: 438/700
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence

Abstract

An amorphous material containing silicon, carbon, hydrogen and nitrogen, provides a barrier/etch stop layer for use with low dielectric constant insulating layers and copper interconnects. The amorphous material is prepared by plasma assisted chemical vapor deposition (CVD) of alklysilanes together with nitrogen and ammonia. Material that at the same time has a dielectric constant less than 4.5, an electrical breakdown field about 5 MV/cm, and a leakage current less than or on the order of 1 nA/cm² at a field strength of 1 MV/cm has been obtained. The amorphous material meets the requirements for use as a barrier/etch stop layer in a standard damascene fabrication process.

Claims

1. A method of fabricating an integrated circuit device, the method comprising:

depositing a layer of amorphous material comprising silicon, carbon, nitrogen, and hydrogen by chemical vapor deposition on a substrate, the substrate comprising regions of metal conductor and regions of insulating material;

depositing a layer of insulating material on the amorphous layer; and

etching patterns in the layer of insulating material wherein the amorphous layer etches at a slower rate than the layer of insulating material.

2. The method of claim 1 wherein the amorphous material comprises between about 15% and about 40% silicon, between about 20% and about 40% carbon, between about 25% and about 55% hydrogen and between about 2% and about 20% nitrogen.

3. The method of claim 1 wherein the amorphous material responds to a fluorocarbon etch at a rate that is at least two times slower than the rate at which the layer of insulating material responds.

4. The method of claim 1 wherein the insulating material is a low dielectric constant material.

5. The method of claim 2 wherein the layer of amorphous material is deposited using process gases comprising an alkylsilane, nitrogen, and ammonia.

6. The method of claim 5 wherein the alkylsilane is tetramethylsilane and the ratio of the sum of the flow rate of nitrogen and ammonia to the flow rate of tetramethylsilane is between about 0.25:

1 and about 2.75;

1.

7. The method of claim 6 wherein the flow rate of ammonia is at least about 15% of the sum of the flow rates of nitrogen and ammonia.

8. The method of claim 5 wherein the layer of amorphous material has a dielectric constant less than about 6 and does not experience electrical breakdown at a field strength of 5 MV/cm.

9. The method of claim 8 wherein the layer of amorphous material has a density of at least about 1.6 g/cm³ and a hardness of at least about 8 gigapascals.

10. The method of claim 1 further comprising:

filling the etched patterns in the layer of insulating material with metal; and

depositing a layer of amorphous material comprising silicon, carbon, nitrogen, and hydrogen by chemical vapor deposition on the metal filled layer of insulating material.

11. The method of claim 1 further comprising depositing an etch stop layer comprising silicon, carbon, nitrogen, and hydrogen by chemical vapor deposition on the layer of insulating material;

depositing a trench level layer of insulating material on the etch stop layer, and

etching a via pattern in the trench level layer of insulating material wherein the etch stop layer etches at a rate that is slower than the rate at which the trench level layer of insulating material etches.

12. An integrated circuit device comprising:

a first level substrate comprising regions of metal conductor and regions of insulating material;

a layer of amorphous material comprising silicon, carbon, nitrogen, and hydrogen overlying the substrate; and

a second level layer of insulating material overlying the layer of amorphous material, wherein the amorphous material etches at a rate that is slower than the rate at which the layer of insulating material etches.

13. The device of claim 12 wherein the amorphous material comprises between about 15% and about 40% silicon, between about 20% and about 40% carbon, between about 25% and about 55% hydrogen and between about 2% and about 20% nitrogen.

14. The device of claim 13 wherein the amorphous material has a dielectric constant about 6 or below.

15. The device of claim 14 wherein the amorphous material has a dielectric constant less than about 4.5 and does not experience electrical breakdown at a field strength of 5 MV/cm.

16. The device of claim 14 wherein the amorphous material has a density of at least about 1.6 g/cm³ and a hardness of at least about 8 gigapascals.

17. The device of claim 12 wherein the second level layer of insulating material comprises patterns filled with metal.

18. The device of claim 17 wherein the metal is copper.

19. The device of claim 17 further comprising a layer of amorphous material comprising silicon, carbon, nitrogen, and hydrogen overlying the second level layer of insulating material.

20. The device of claim 12 wherein the device comprises regions wherein insulating material in the second level layer of insulating material is separated from a region of metal conductor in the first level substrate by the layer of amorphous material and wherein the layer of amorphous material serves as a barrier to migration of metal from the region of metal conductor in the first level substrate.

21. The device of claim 12 wherein the second level layer of insulating material comprises silicon dioxide.

22. The device of claim 12 wherein the second level layer of insulating material comprises a low dielectric constant insulating material.

23. A method of producing an etch stop layer on a substrate, the method comprising:

introducing the substrate into a reactor;

providing a flow of process gases comprising an alkylsilane, nitrogen, and ammonia to the reactor wherein the ratio of the sum of the flow rate of nitrogen and ammonia to the flow rate of alkylsilane is between about 0.25;

1 and about 2.75;

1;

producing a plasma condition in the reactor wherein reaction of the process gases results in deposition of the etch stop layer on the substrate.

24. The method of claim 23 wherein the etch stop layer is an amorphous material comprising between about 15% and about 40% silicon, between about 20% and about 40% carbon, between about 25% and about 55% hydrogen and between about 2% and about 20% nitrogen.

25. The method of claim 23 wherein the alkylsilane is tetramethylsilane and the ratio of the sum of the flow rate of nitrogen and ammonia to the flow rate of tetramethylsilane is between about 1.1:

1 and 1.6;

1.

26. The method of claim 25 wherein the flow rate of ammonia is at least about 15% of the sum of the flow rates of nitrogen and ammonia

27. The method of claim 23 wherein the etch stop layer has a dielectric constant about 6 or below.

28. The method of claim 27 wherein the etch stop layer has a dielectric constant less than about 4.5 and does not experience electrical breakdown at a field strength of 5 MV/cm.

29. The method of claim 27 wherein the etch stop layer has a density of at least about 1.6 g/cm³ and a hardness of at least about 8 gigapascals.