System and method for fail-over memory

• US 20030037278A1
• Filed: 07/31/2002
• Published: 02/20/2003
• Est. Priority Date: 07/16/1998
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Information Technologies Group LP (HP Inc.)
• Inventors: Olarig, Sompong Paul
• Granted Patent: US 7,100,071 B2
• Time in Patent Office: Days
• US Class Current: 714/5
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A fail-over system for memory is provided. The fail-over system for memory includes a virtual channel memory controller providing one or more virtual channel memories in a memory array. A memory fail-over controller coupled to the virtual channel memory controller provides memory fail-over data to the virtual channel memory controller. The virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fail-over data.

Claims

1. A fail-over system for memory comprising:

a virtual channel memory controller providing one or more virtual channel memories in a memory array;

a memory fail-over controller coupled to the virtual channel memory controller, the memory fail-over controller providing memory fail-over data to the virtual channel memory controller; and

wherein the virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fail-over data.

2. The fail-over system of claim 1 wherein the memory fail-over controller further comprises a fail-over status system generating status data that indicates the virtual channel memories that are being used as fail-over memory channels.

3. The fail-over system of claim 1 wherein the memory fail-over controller further comprises a memory remapping system generating fail-over memory channel address data that corresponds to one or more failed memory locations in the memory array.

4. The fail-over system of claim 1 wherein the memory fail-over controller further comprises an error indication system generating error indication data in response to the memory fail-over data.

5. The fail-over system of claim 1 wherein the memory fail-over controller further comprises a memory stall system stalling access to the fail-over memory channels.

6. The fail-over system of claim 5 wherein the memory stall system implements a prefetch command.

7. The fail-over system of claim 1 wherein the memory fail-over controller further comprises a virtual channel memory controller interface.

8. The fail-over system of claim 1 wherein the virtual channel memory controller further comprises a replacement system with fail-over detect.

9. The fail-over system of claim 1 wherein the virtual channel memory controller further comprises a write system with fail-over detect.

10. A method for providing a fail-over memory comprising:

detecting a memory failure condition for one or more memory cells;

redesignating a virtual channel memory as a fail-over memory; and

remapping the address of the one or more memory cells to the address for the fail-over memory.

11. The method of claim 10 wherein detecting a memory failure condition for the one or more memory cells comprises detecting an incipient failure.

12. The method of claim 11 further comprising transferring data stored in the one or more memory cells to the fail-over memory.

13. The method of claim 12 further comprising stalling requests to the one or more memory cells while transferring the data stored in the one or more memory cells to the fail-over memory.

14. The method of claim 10 wherein detecting a memory failure condition for the one or more memory cells comprises detecting excessive ECC error codes.

15. The method of claim 10 wherein detecting a memory failure condition for the one or more memory cells comprises detecting a catastrophic failure.

16. The method of claim 10 wherein remapping the address of the one or more memory cells to the address for the fail-over memory comprises remapping the address in a virtual channel memory controller.

17. The method of claim 10 wherein remapping the address of the one or more memory cells to the address for the fail-over memory comprises remapping the address in a memory fail-over controller.

18. The method of claim 10 further comprising generating a notification that the virtual channel memory is operating as a fail-over memory.

19. A method for providing a fail-over memory comprising:

detecting an incipient memory failure condition for one or more memory cells;

redesignating an active auxiliary memory as a fail-over memory;

remapping the address of the one or more memory cells to the address for the fail-over memory;

transferring data stored in the one or more memory cells to the fail-over memory;

stalling requests to the one or more memory cells while transferring the data stored in the one or more memory cells to the fail-over memory; and

generating a notification that the active auxiliary memory is operating as a fail-over memory.

20. The method of claim 19 wherein the active auxiliary memory is a virtual channel memory.