Computer memory error management system and method

• US 20030037280A1
• Filed: 08/20/2001
• Published: 02/20/2003
• Est. Priority Date: 08/20/2001
• Status: Abandoned Application

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Berg, Jerry D., Choy, Marian M.
• Application Number:
  US09/933,603
• Publication Number:
  US 20030037280A1
• Time in Patent Office: Days
• US Class Current: 714/6
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 21/556 involving covert channels, i.e. data leakage between processes inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755

Abstract

The present invention is a computer memory error management system and method that facilitates fault tolerant memory I/O in a manner that permits smooth and continuous operations. The system and method handles memory control buffer corruption concerns associated with memory errors and corrects single bit errors. Information is placed in a memory controller buffer and a determination is made if a correctable error or non-correctable error exists in the information. If the error is a correctable error it is corrected in-line. A memory cell error resolution process is performed and information is rewritten to a memory control buffer location. If rewriting to the same memory controller buffer location does not solve the error, a hard error handling process is performed. A hard error handling process and a non-correctable error handling process utilize a fail over process in which an alternate memory controller performs the I/O operations.

Claims

9. A memory controller comprising:

a communication bus for communicating information between components of said memory controller;

a controller processing core for directing operations of said memory controller and providing a platform to implement a memory error management process, said controller coupled to said communication bus;

an XOR array for providing correction of single bit errors, said XOR array coupled to said communications bus;

a memory controller buffer for storing information being communicated by said memory controller between a host and a physical memory medium, said controller buffer coupled to said XOR array;

a backend interface for providing a communications interface to back end components, said backend interface coupled to said communications bus; and

a front end interface for providing a communications interface to front end components, said front end interface coupled to said communications bus.

10. A memory controller of claim 9 wherein an error is detected at a location within said memory controller buffer and said controller processing core directs rewriting information to said location and rechecking for an error in said location.

11. A memory controller of claim 10 wherein said controller processing core directs a reread of information from a physical memory medium and the reread information is utilized in said rewrite to said location.

12. A memory controller of claim 10 wherein said controller processing core fences off said location and rewrites said information to a different location within said memory controller buffer.

13. A memory controller of claim 9 wherein an error is detected and said controller processing core relinquishes responsibility for master control operations to an alternate memory controller.

14. A memory controller of claim 13 wherein an overall memory input/output operation that resulted in said error is treated as not complete and said processing core relinquishes responsibility for master control operations to an alternate memory controller that completes said overall memory input/output operation

15. A memory controller of claim 9 wherein said controller processing core receives responsibility for master control operations from another memory controller and processes a memory input/output operation request that produced an unrecoverable error.

16. A memory controller of claim 9 further comprising an accumulator for storing information associated with the logic and arithmetic operations of said XOR array, said accumulator coupled to said XOR array.

18. A memory error resolution process comprising:

receiving information indicating whether an error is a correctable error or a non-correctable error;

performing a memory controller buffer refreshing process;

engaging in a correctable error handling process; and

performing a non-correctable error handling process.

1. A memory error management method comprising:

attempting to access information in an error checking and correction memory;

determining if an error exists in the information;

deciding if an error is correctable or not correctable;

engaging in an error correction process; and

performing a memory cell error resolution process.

2. The memory error management method of claim 1 wherein said information is a plurality of bits in a memory controller buffer cell.

3. The memory error management method of claim 1 wherein said error checking and correction memory is a memory controller buffer of a disk array memory system.

4. The memory error management method of claim 1 wherein said error correction process is a single bit error correction code process that corrects a single bit error inline.

5. The memory error management method of claim 1 wherein a hamming code and error syndrome is utilized to correct a bit in error.

6. The memory error management method of claim 1 wherein said memory cell error resolution process includes rewriting information to a memory control buffer location.

7. The memory error management method of claim 1 wherein said memory cell error resolution process includes rewriting corrected information to a memory controller buffer location and if said rewriting resolves the error a soft correctable error count is incremented.

8. The memory error management method of claim 1 wherein said memory cell error resolution process includes a memory controller fail over process in which an alternate memory controller buffer takes over master responsibilities associated with an overall memory input/output operation.

17. The memory controller of claim 7 wherein said controller processing core directs tracking of error information including counts of soft correctable errors, hard correctable errors and non-correctable errors.

19. A memory error resolution process of claim 18 wherein said memory controller buffer refreshing process comprises re-entering corrected information into said memory controller buffer location.

20. A memory error resolution process of claim 19 wherein a soft correctable error handling process is engaged if no errors exist after said re-checking information in said memory controller buffer.

21. A memory error resolution process of claim 20 wherein a soft correctable error handling process comprises tracking soft correctable error information including incrementing a soft error correctable count.

22. A memory error resolution process of claim 19 wherein a hard correctable error handling process is implemented if an errors exist after said re-checking information in said memory controller buffer, said hard correctable error handling process includes an error fail-over process that utilizes resources of a different or alternate memory controller buffer

23. A memory error resolution process of claim 19 wherein said non-correctable error handling process comprises an error fail-over process in which an initial memory controller that had control when a memory I/O operation resulted in a memory error relinquishes control to an alternate memory controller and said alternate memory controller attempts to complete said memory I/O operation.

24. A memory error resolution process of claim 18 further comprising performing a recursive error handling process.

25. A memory error resolution process of claim 18 further comprising performing a predictive failure analysis process.

22-1. A memory error resolution process of claim 19 wherein said non correctable error handling process comprises:

fencing off of a memory controller buffer location; and

forwarding the information to another location within a memory controller buffer.