Method for manufacturing and structure of transistor with low-k spacer

• US 20030038305A1
• Filed: 08/08/2002
• Published: 02/27/2003
• Est. Priority Date: 08/21/2001
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wasshuber, Christoph A.
• Application Number:
  US10/214,667
• Publication Number:
  US 20030038305A1
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for manufacturing a transistor includes forming a gate dielectric layer adjacent a semiconductor substrate. A gate electrode may be formed covering at least a portion of the gate dielectric layer. First and second doped regions of the semiconductor substrate may be formed proximate the gate electrode and separated by a channel region. First and second spacers may be formed at least partially in contact with the gate electrode. The first and second spacers may each comprise a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide. Third and fourth doped regions of the semiconductor substrate may be formed proximate the first and second spacers, respectively.

Claims

1. A method for manufacturing a transistor of a semiconductor device, comprising:

forming a gate dielectric layer adjacent a semiconductor substrate;

forming a gate electrode covering at least a portion of the gate dielectric layer;

forming first and second doped regions of the semiconductor substrate proximate the gate electrode, the first and second doped regions separated by a channel region;

forming first and second spacers at least partially in contact with the gate electrode, the first and second spacers each comprising a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide; and

forming third and fourth doped regions of the semiconductor substrate proximate the first and second spacers, respectively.

2. The method of claim 1, further comprising:

forming first and second cap layers at least partially in contact with first and second spacers, respectively; and

wherein first and second cap layers each comprise a material having a dielectric coefficient value equal to or greater than the dielectric coefficient value of silicon dioxide.

3. The method of claim 2, further comprising forming a silicide layer of the semiconductor substrate proximate the first and second spacers.

4. The method of claim 1, further comprising forming an oxide layer of the semiconductor substrate proximate the first and second spacers.

5. The method of claim 1, further comprising forming first and second contacts proximate first and second spacers, respectively.

6. The method of claim 1, wherein the dielectric coefficient value of the material is less than approximately 4.2.

7. The method of claim 1, wherein the first and second spacers comprise parylene.

8. The method of claim 2, wherein the first and second cap layers comprise silicon nitride.

9. A method for manufacturing a transistor of a semiconductor device, comprising:

forming a gate dielectric layer adjacent a semiconductor substrate;

forming a gate electrode covering at least a portion of the gate dielectric layer;

forming first and second spacers at least partially in contact with the gate electrode, the first and second spacers each comprising a material having a dielectric coefficient value equal to or greater than the dielectric coefficient value of silicon dioxide;

forming first and second doped regions of the semiconductor substrate proximate the first and second spacers, respectively;

removing the first and second spacers;

forming third and fourth doped regions of the semiconductor substrate proximate the gate electrode, the third and fourth doped regions separated by a channel region; and

forming third and fourth spacers at least partially in contact with the gate electrode, the third and fourth spacers each comprising a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide.

10. The method of claim 9, further comprising:

forming first and second cap layers at least partially in contact with third and fourth spacers, respectively; and

wherein first and second cap layers each comprise a material having a dielectric coefficient value equal to or greater than the dielectric coefficient value of silicon dioxide.

11. The method of claim 10, further comprising forming a silicide layer of the semiconductor substrate proximate the third and fourth spacers.

12. The method of claim 9, further comprising forming an oxide layer of the semiconductor substrate proximate the third and fourth spacers.

13. The method of claim 9, further comprising forming first and second contacts proximate the third and fourth spacers.

14. The method of claim 9, wherein the dielectric coefficient value of the material is less than approximately 4.2.

15. The method of claim 9, wherein the third and fourth spacers comprise parylene.

16. The method of claim 9, wherein the first and second spacers comprise silicon nitride.

17. The method of claim 10, wherein the first and second cap layers comprise silicon nitride.

18. A transistor assembly, comprising:

a gate dielectric layer disposed upon a semiconductor substrate;

a gate electrode disposed at least partially upon the gate dielectric layer;

first and second doped regions of the semiconductor substrate proximate the gate electrode, the first and second doped regions separated by a channel region;

first and second spacers at least partially in contact with the gate electrode, the first and second spacers each comprising a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide;

third and fourth doped regions of the semiconductor substrate proximate the first and second spacers, respectively; and

first and second cap layers at least partially in contact with third and fourth spacers, respectively, the first and second cap layers each comprising a material having a dielectric coefficient value equal to or greater than the dielectric coefficient value of silicon dioxide.

19. The transistor assembly of claim 18, further comprising a silicide layer proximate the first and second spacers.

20. The transistor assembly of claim 18, further comprising an oxide layer proximate the first and second spacers.

21. The transistor assembly of claim 18, further comprising first and second contacts proximate first and second spacers, respectively.

22. The transistor assembly of claim 18, wherein the dielectric coefficient value of the material is less than approximately 4.2.

23. The transistor assembly of claim 18, wherein the first and second spacers comprise parylene.