Method for manufacturing and structure of transistor with low-k spacer
First Claim
1. A method for manufacturing a transistor of a semiconductor device, comprising:
- forming a gate dielectric layer adjacent a semiconductor substrate;
forming a gate electrode covering at least a portion of the gate dielectric layer;
forming first and second doped regions of the semiconductor substrate proximate the gate electrode, the first and second doped regions separated by a channel region;
forming first and second spacers at least partially in contact with the gate electrode, the first and second spacers each comprising a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide; and
forming third and fourth doped regions of the semiconductor substrate proximate the first and second spacers, respectively.
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Accused Products
Abstract
A method for manufacturing a transistor includes forming a gate dielectric layer adjacent a semiconductor substrate. A gate electrode may be formed covering at least a portion of the gate dielectric layer. First and second doped regions of the semiconductor substrate may be formed proximate the gate electrode and separated by a channel region. First and second spacers may be formed at least partially in contact with the gate electrode. The first and second spacers may each comprise a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide. Third and fourth doped regions of the semiconductor substrate may be formed proximate the first and second spacers, respectively.
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Citations
23 Claims
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1. A method for manufacturing a transistor of a semiconductor device, comprising:
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forming a gate dielectric layer adjacent a semiconductor substrate;
forming a gate electrode covering at least a portion of the gate dielectric layer;
forming first and second doped regions of the semiconductor substrate proximate the gate electrode, the first and second doped regions separated by a channel region;
forming first and second spacers at least partially in contact with the gate electrode, the first and second spacers each comprising a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide; and
forming third and fourth doped regions of the semiconductor substrate proximate the first and second spacers, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for manufacturing a transistor of a semiconductor device, comprising:
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forming a gate dielectric layer adjacent a semiconductor substrate;
forming a gate electrode covering at least a portion of the gate dielectric layer;
forming first and second spacers at least partially in contact with the gate electrode, the first and second spacers each comprising a material having a dielectric coefficient value equal to or greater than the dielectric coefficient value of silicon dioxide;
forming first and second doped regions of the semiconductor substrate proximate the first and second spacers, respectively;
removing the first and second spacers;
forming third and fourth doped regions of the semiconductor substrate proximate the gate electrode, the third and fourth doped regions separated by a channel region; and
forming third and fourth spacers at least partially in contact with the gate electrode, the third and fourth spacers each comprising a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A transistor assembly, comprising:
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a gate dielectric layer disposed upon a semiconductor substrate;
a gate electrode disposed at least partially upon the gate dielectric layer;
first and second doped regions of the semiconductor substrate proximate the gate electrode, the first and second doped regions separated by a channel region;
first and second spacers at least partially in contact with the gate electrode, the first and second spacers each comprising a material having a dielectric coefficient value less than the dielectric coefficient value of silicon dioxide;
third and fourth doped regions of the semiconductor substrate proximate the first and second spacers, respectively; and
first and second cap layers at least partially in contact with third and fourth spacers, respectively, the first and second cap layers each comprising a material having a dielectric coefficient value equal to or greater than the dielectric coefficient value of silicon dioxide. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification