Semiconductor integrated circuit

• US 20030038664A1
• Filed: 08/19/2002
• Published: 02/27/2003
• Est. Priority Date: 08/21/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Fujimaki, Osamu, Ootake, Toshikazu
• Granted Patent: US 6,664,839 B2
• Time in Patent Office: Days
• US Class Current: 327/295
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

In a semiconductor integrated circuit having a first circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n) each of which is delayed by a delay time of i×T (T is a constant time) from a reference signal, and a second circuit which carries out signal processing using n clock signals input from the first circuit via n signal wirings, for at least a part of the n signal wirings, the positions of the edges of two clock signals transmitted on the two adjacent signal wirings are separated, as seen on the time base, by more than T in the time.

Claims

1. In a semiconductor integrated circuit comprising a first circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n) each delayed by a delay time of i×

T (T is a constant time) from a reference signal, and a second circuit which carries out signal processing using said n clock signals from the first circuit via n signal wirings, wherein, for at least a part of said n signal wirings, the positions of edges of two of said clock signals transmitted on adjacent two of said signal wirings as seen on the time base are separated in time larger than the time T.

2. In the semiconductor integrated circuit as claimed in claim 1, further comprising a buffer insert circuit provided between said first circuit and said second circuit and is equipped with n buffers corresponding to said n clock signals, where said signal wirings consist of n input wirings which transmit said n clock signals from said first circuit to said n buffers and n output wirings which transmit said n clock signals from said n buffers to said second circuit, and at least a part of said n buffers are arranged so as to have the positions of edges of two of said clock signals transmitted on two of adjacent input wirings or output wirings are separated by a time larger than the time T as seen on the time base.

3. The semiconductor integrated circuit as claimed in claim 2, wherein said n buffers are arranged one-dimensionally.

4. The semiconductor integrated circuit as claimed in claim 2, wherein said n buffers are arranged two-dimensionally clockwise or counterclockwise.

5. The semiconductor integrated circuit as claimed in claim 4, wherein said n input wirings are laid to a point in the central part of the region where said n buffers are arranged, and is laid from the point in the central part to the input terminals of corresponding buffers so as to have mutually equal wiring lengths, and said n output wirings are laid from output terminals of respective buffers to the point in the central part so as to have equal wiring lengths, and are laid from the point in the central part to said second circuit.

6. Te semiconductor integrated circuit as claimed in claim 4, wherein said n input wirings are laid so as to have equal wiring lengths in the X direction from said first circuit and are laid further to the input terminals of corresponding buffers so as to have mutually equal wiring lengths in the Y direction, and said n output wirings are laid from the output terminals of corresponding buffers so as to have mutually equal wiring lengths in the Y direction and are laid further to said second circuit so as to have equal wiring lengths in the X direction.