Flash memory having a flexible bank partition
First Claim
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1. A method of forming a simultaneous operation dual-bank flash memory device, said method comprising the steps of:
- providing a plurality of flash memory arrays;
providing row and column decoders for each flash memory array; and
partitioning the plurality of flash memory arrays into a first memory bank and a second memory bank by coupling first bank row and column address lines between first bank row and column pre-decoders and the row and column decoders associated with the first memory bank, and by coupling second bank row and column address lines between second bank row and column pre-decoders and the row and column decoders associated with the second memory bank.
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Abstract
A simultaneous operation flash memory chip architecture having a flexible memory bank partition for forming first and second memory banks from a plurality of flash memory arrays, said partition being defined by selecting one of a plurality of preformed metal masks, which allows the formation and extension of pre-decoded address lines to inputs of decoders associated with the first and second memory banks, respectively.
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Citations
10 Claims
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1. A method of forming a simultaneous operation dual-bank flash memory device, said method comprising the steps of:
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providing a plurality of flash memory arrays;
providing row and column decoders for each flash memory array; and
partitioning the plurality of flash memory arrays into a first memory bank and a second memory bank by coupling first bank row and column address lines between first bank row and column pre-decoders and the row and column decoders associated with the first memory bank, and by coupling second bank row and column address lines between second bank row and column pre-decoders and the row and column decoders associated with the second memory bank.
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2. A method of forming a dual-bank flash memory device, said method comprising the steps of:
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providing a plurality of flash memory arrays, each memory array having associated row and column address decoders; and
partitioning the flash memory arrays into a first memory bank and a second memory bank by;
forming first bank pre-decoded column address lines and coupling them between a first bank column address pre-decoder and the column address decoders associated with the first bank, forming second bank pre-decoded column address lines and coupling them between a second bank column address pre-decoder and the column address decoders associated with the second bank, forming first bank pre-decoded row address lines and coupling them between a first bank row address pre-decoder and the row address decoders associated with the first bank, and forming second bank pre-decoded row address lines and coupling them between a second bank row address pre-decoder and the row address decoders associated with the second bank. - View Dependent Claims (3, 4)
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5. A simultaneous operation flash memory chip having a flexible memory bank partition, comprising:
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a plurality of memory arrays having associated row and column decoders, said plurality of memory arrays partitioned into first and second memory banks;
a first bank column address pre-decoder coupled to the column address decoders associated with the first memory bank;
a first bank row address pre-decoder coupled to the row address decoders associated with the first memory bank;
a second bank column address pre-decoder coupled to the column address decoders associated with the second memory bank; and
a second bank row address pre-decoder coupled to the row address decoders associated with the second memory bank. - View Dependent Claims (6, 7, 8)
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9. A simultaneous operation flash memory device having a flexible dual-bank architecture, comprising:
- a plurality of memory arrays capable of being partitioned into a first memory bank and a second memory bank, the partitioning of arrays within the first and second memory banks determined by how pre-decoded row and address lines are formed during a process used to fabricate the device.
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10. A method of forming a simultaneous operation flash memory device having a flexible memory bank partition, said method comprising the steps of:
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providing a plurality of flash memory arrays, each memory array having associated row and column address decoders; and
partitioning the plurality of flash memory arrays into a first memory bank and a second memory bank by;
coupling first bank row and column address lines between first bank row and column pre-decoders and the row and column decoders associated with the first memory bank and coupling second bank row and column address lines between second bank row and column pre-decoders and the row and column decoders associated with the second memory bank, wherein the step of partitioning is performed by selecting from a plurality of preformed metal masks, said plurality of metal masks being distinguished from one other by variances in pre-decoded address line patterns.
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Specification