Semiconductor device and method of fabricating the same

• US 20030040158A1
• Filed: 08/21/2002
• Published: 02/27/2003
• Est. Priority Date: 08/21/2001
• Status: Abandoned Application

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Saitoh, Takehiro
• Application Number:
  US10/224,959
• Publication Number:
  US 20030040158A1
• Time in Patent Office: Days
• US Class Current: 438/279
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device improves the electron mobility in the n-channel MOSFET and reduces the bend or warp of the semiconductor substrate or wafer. The fist nitride layer having a tensile stress is formed on the substrate to cover the n-channel MOSFET. The tensile stress of the first nitride layer serves to relax a compressive stress existing in the channel region. The second nitride layer having an actual compressive stress is formed on the substrate to cover the p-channel MOSFET. The first and second nitride layers serve to decrease bend or warp of the substrate. Preferably, the first nitride layer is a nitride layer of Si formed by a LPCVD process, and the second nitride layer is a nitride layer of Si formed by a PECVD process.

Claims

1. A semiconductor device comprising:

a Si substrate;

a n-channel MOSFET formed on the substrate;

a first nitride layer formed to cover the n-channel MOSFET;

the first nitride layer containing tensile stress;

a p-channel MOSFET formed on the substrate;

a second nitride layer formed to cover the p-channel MOSFET; and

the second nitride layer containing compressive stress.

2. The device according to claim 1, wherein each of the n-channel MOSFET and the p-channel MOSFETs comprises source/drain regions, a gate dielectric layer, a gate electrode, sidewall spacers, and silicide layers formed in a top of the gate electrode and in surfaces of the source/drain regions;

and wherein the first nitride layer covers the source/drain regions, the gate dielectric layer, the gate electrode, the sidewall spacers, and the silicide layers of the n-channel MOSFET;

and wherein the second nitride layer covers the source/drain regions, the gate dielectric layer, the gate electrode, the sidewall spacers, and the silicide layers of the p-channel MOSFET.

3. The device according to claim 1, wherein the first nitride layer is formed by a LPCVD process.

4. The device according to claim 1, wherein the second nitride layer is formed by a PECVD process.

5. The device according to claim 1, wherein the n-channel MOSFET has a channel region in a surface area of the substrate;

and wherein the tensile stress of the first nitride layer serves to relax a compressive stress existing in the channel region.

6. The device according to claim 1, wherein the first nitride layer and the second nitride layer serve to decrease bend or warp of the substrate.

7. A semiconductor device comprising:

a Si substrate;

a n-channel MOSFET formed on the substrate;

a first nitride layer formed to cover the n-channel MOSFET;

the first nitride layer containing tensile stress;

a p-channel MOSFET formed on the substrate;

a second nitride layer formed to cover the p-channel MOSFET and the first nitride layer; and

the second nitride layer containing compressive stress.

8. The device according to claim 7, wherein each of the n-channel MOSFET and the p-channel MOSFETs comprises source/drain regions, a gate dielectric layer, a gate electrode, sidewall spacers, and silicide layers formed in a top of the gate electrode and in surfaces of the source/drain regions;

and wherein the first nitride layer covers the source/drain regions, the gate dielectric layer, the gate electrode, the sidewall spacers, and the silicide layers of the n-channel MOSFET;

and wherein the second nitride layer covers the source/drain regions, the gate dielectric layer, the gate electrode, the sidewall spacers, and the silicide layers of the p-channel MOSFET.

9. The device according to claim 7, wherein the first nitride layer is formed by a LPCVD process.

10. The device according to claim 7, wherein the second nitride layer is formed by a PECVD process.

11. The device according to claim 7, wherein the n-channel MOSFET has a channel region in a surface area of the substrate;

and wherein the tensile stress of the first nitride layer serves to relax a compressive stress existing in the channel region.

12. The device according to claim 7, wherein the first nitride layer and the second nitride layer serve to decrease bend or warp of the substrate.

13. A method of fabricating a semiconductor device, comprising the steps of:

forming a n-channel MOSFET and a p-channel MOSFET on a semiconductor substrate;

forming a first nitride layer over the substrate to cover the n-channel MOSFET and the p-channel MOSFET, the first nitride layer containing tensile stress;

selectively removing a part of the first nitride layer in a corresponding area to the p-channel MOSFET;

forming a second nitride layer over the substrate to cover the n-channel MOSFET and the p-channel MOSFET, the second nitride layer containing compressive stress; and

selectively removing a part of the second nitride layer in a corresponding area to the n-channel MOSFET.

14. The method according to claim 13, wherein each of the n-channel MOSFET and the p-channel MOSFETs comprises source/drain regions, a gate dielectric layer, a gate electrode, sidewall spacers, and silicide layers formed in a top of the gate electrode and in surfaces of the source/drain regions;

and wherein the first nitride layer covers the source/drain regions, the gate dielectric layer, the gate electrode, the sidewall spacers, and the silicide layers of the n-channel MOSFET;

and wherein the second nitride layer covers the source/drain regions, the gate dielectric layer, the gate electrode, the sidewall spacers, and the silicide layers of the p-channel MOSFET.

15. The method according to claim 13, wherein the first nitride layer is formed by a LPCVD process.

16. The method according to claim 13, wherein the second nitride layer is formed by a PECVD process.

17. A method of fabricating a semiconductor device, comprising the steps of:

forming a n-channel MOSFET and a p-channel MOSFET on a semiconductor substrate;

forming a first nitride layer over the substrate to cover the n-channel MOSFET and the p-channel MOSFET, the first nitride layer containing tensile stress;

selectively removing a part of the first nitride layer in a corresponding area to the p-channel MOSFET; and

forming a second nitride layer over the substrate to cover the n-channel MOSFET and the p-channel MOSFET, the second nitride layer containing compressive stress.

18. The method according to claim 17, wherein each of the n-channel MOSFET and the p-channel MOSFETs comprises source/drain regions, a gate dielectric layer, a gate electrode, sidewall spacers, and silicide layers formed in a top of the gate electrode and in surfaces of the source/drain regions;

and wherein the first nitride layer covers the source/drain regions, the gate dielectric layer, the gate electrode, the sidewall spacers, and the silicide layers of the n-channel MOSFET;

and wherein the second nitride layer covers the source/drain regions, the gate dielectric layer, the gate electrode, the sidewall spacers, and the silicide layers of the p-channel MOSFET.

19. The method according to claim 17, wherein the first nitride layer is formed by a LPCVD process.

20. The method according to claim 17, wherein the second nitride layer is formed by a PECVD process.