Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment

• US 20030041216A1
• Filed: 08/05/2002
• Published: 02/27/2003
• Est. Priority Date: 08/27/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Rosenbluth, Mark B., Wolrich, Gilbert
• Granted Patent: US 7,216,204 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

Stored units of information related to packet processing are associated with identifiers, each of which is maintained as an entry in a Content Addressable Memory (CAM). Each entry includes status information associated with the information unit with which the identifier is associated. The status information is used to determine validity of the information unit with which the status information is associated.

Claims

1. A method of accessing shared-access information stored in memory comprising:

storing units of information related to packet processing, each unit having an associated identifier;

maintaining each identifier as an entry in a Content Addressable Memory (CAM), each entry including status information associated with the information unit with which the identifier is associated; and

using the status information to determine validity of the information unit with which the status information is associated.

2. The method of claim 1 wherein the status information comprises:

a lock status to indicate that the information unit with which the status information is associated is in the process of being modified.

3. The method of claim 1 wherein the information units are information units stored in a cache, the cached information units collectively corresponding to a portion of all such information units stored in memory.

4. The method of claim 3 wherein the information units are queue descriptors.

5. The method of claim 4 wherein the associated identifiers are queue numbers.

6. The method of claim 1 wherein the information units correspond to information in state tables.

7. The method of claim 6 wherein the associated identifiers are packet flow identifiers.

8. The method of claim 3, further comprising:

performing a lookup in the CAM of a selected one of the information units stored in the memory based on the associated identifier; and

receiving from the CAM a lookup result that indicates if a match was found, a match indicating that the selected one of the information units is one of the cached information units.

9. The method of claim 5 wherein the lookup result includes the status information of the matched identifier.

10. The method of claim 8 wherein the CAM maintains a Least Recently Used (LRU) list of the identifiers in the CAM and, if no match is found, the result providing an index to an identifier from the LRU list.

11. The method of claim 10, further comprising using the LRU identifier to replace one of the cached information units with the selected one of the information units from memory.

12. The method of claim 11, further comprising:

replacing the LRU identifier in the CAM with the identifier associated with the selected one of the information units.

13. The method of claim 8, further comprising:

setting the lock status of the identifier associated with the selected one of the information units to indicate invalid status;

modifying the selected one of the information units in the cache; and

upon completion of the modification, changing the lock status to indicate valid status.

14. A computer program product residing on a computer-readable medium comprising instructions to cause a computer to:

store units of information related to packet processing, each unit having an associated identifier;

maintain each identifier as an entry in a Content Addressable Memory (CAM), each entry including status information associated with the information unit with which the identifier is associated; and

use the status information to determine validity of the information unit with which the status information is associated.

15. A computer program product of claim 14, wherein the information units are information units stored in a cache, the cached information units collectively corresponding to a portion of all such information units stored in memory.

16. An apparatus comprising:

a processor;

a memory storing a computer program product residing on a computer-readable medium comprising instructions to cause a computer to;

store units of information related to packet processing, each unit having an associated identifier;

maintain each identifier as an entry in a Content Addressable Memory (CAM), each entry including status information associated with the information unit with which the identifier is associated; and

use the status information to determine validity of the information unit with which the status information is associated.

17. The apparatus of claim 16 wherein the information units are information units stored in a cache, the cached information units collectively corresponding to a portion of all such information units stored in memory.