Multithreaded microprocessor with register allocation based on number of active threads

• US 20030041228A1
• Filed: 08/05/2002
• Published: 02/27/2003
• Est. Priority Date: 08/27/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Rosenbluth, Mark B., Wolrich, Gilbert
• Granted Patent: US 7,487,505 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.

Claims

1. A method of allocating resources in a multithreaded processor comprising:

providing resources for use by execution threads supported by the multithreaded processor; and

applying configuration information to a selection of the resources to allocate the resources among active ones of the execution threads.

2. The method of claim 1 wherein the resources comprise:

registers in a general purpose register file.

3. The method of claim 1 wherein the configuration information comprises:

a configuration bit which when cleared indicates all of the supported execution threads as the active ones and when set indicates a portion of the supported execution threads as the active ones.

4. The method of claim 1 wherein the configuration information comprises:

a configuration bit which when cleared indicates all of the supported execution threads as the active ones and when set indicates half of the supported execution threads as the active ones.

5. The method of claim 3, wherein the configuration bit resides in a control and status register.

6. The method of claim 2 wherein the general purpose register file includes an address decode portion and a multiplexor coupled to the address decode portion, the multiplexor to receive a thread number and a register number as inputs and to select bits of the thread number and the register number based on the configuration information to form an address corresponding to one of the registers.

7. The method of claim 6 wherein the configuration information indicates selection of all but the least signification bit of the thread number and all bits of the register number.

8. The method of claim 6 wherein the configuration information indicates selection of all but the most significant bit of the register number and all bits of the thread number.

9. The method of claim 6 wherein the selected bits of the register number form a thread-relative register number.

10. A processor comprising:

resources for use by execution threads supported by the processor; and

a resource selector to receive configuration information and to allocate the resources among active ones of the execution threads based on the configuration information.

11. The processor of claim 10 wherein the resources comprise:

registers in a general purpose register file.

12. The processor of claim 10 wherein the configuration information comprises:

a configuration bit which when cleared indicates all of the supported execution threads as the active ones and when set indicates a portion of the supported execution threads as the active ones.

13. The processor of claim 10 wherein the configuration information comprises:

a configuration bit which when cleared indicates all of the supported execution threads as the active ones and when set indicates half of the supported execution threads as the active ones.

14. The processor of claim 12, wherein the configuration bit resides in a control and status register.

15. The processor of claim 11 wherein the general purpose register file includes an address decode portion and the resource selector is a multiplexor coupled to the address decode portion, the multiplexor to receive a thread number and a register number as inputs and to select bits of the thread number and the register number based on the configuration information to form an address corresponding to one of the registers.

16. The processor of claim 15 wherein the configuration information indicates selection of all but the least signification bit of the thread number and all bits of the register number.

17. The processor of claim 15 wherein the configuration information indicates selection of all but the most significant bit of the register number and all bits of the thread number.

18. The processor of claim 15 wherein the selected bits of the register number form a thread-relative register number.