METHOD AND SYSTEM FOR BRANCH TARGET PREDICTION USING PATH INFORMATION
First Claim
1. A system for predicting a branch target for a current branch instruction having a branch address in a processor, the system comprising:
- a register holding a current register value, where at least a portion of the current register value is formed from a first computation, the first computation comprising a first operation on a previous register value and a set of bits from a previous branch address; and
a first table storing branch target values, the first table indexed by the result of second computation on the current register value and the branch address of the current branch instruction.
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Accused Products
Abstract
A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.
31 Citations
31 Claims
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1. A system for predicting a branch target for a current branch instruction having a branch address in a processor, the system comprising:
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a register holding a current register value, where at least a portion of the current register value is formed from a first computation, the first computation comprising a first operation on a previous register value and a set of bits from a previous branch address; and
a first table storing branch target values, the first table indexed by the result of second computation on the current register value and the branch address of the current branch instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for providing a predicted branch target for a current branch instruction, the current branch instruction having an address, the method comprising:
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placing in a register the result of a first calculation on the register and a set of bits from an address of a completed branch instruction;
creating an index by performing a second calculation on the register and a set of bits from the address of the current branch instruction; and
using the index to find a target address for the second branch address in a first table, where the first table either provides a first table prediction for the current branch instruction or returns a first table miss. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A system for predicting a branch target for a current branch address comprising:
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an instruction cache;
an instruction decode unit;
an instruction fetch unit;
a register storing a history value, the history value computed from the XOR operation of the history value and a set of bits from a previous branch address, a shift of the history value, and an OR operation with a set of bits; and
a first cache holding branch target addresses for indirect branches, the first cache accessed by an index, the index being a set of bits from the result of an XOR operation of the history value and the current branch address. - View Dependent Claims (31)
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Specification