Memory controller for multilevel cell memory

• US 20030041299A1
• Filed: 03/15/2002
• Published: 02/27/2003
• Est. Priority Date: 08/23/2001
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Watanabe, Hiroaki, Sekino, Yutaka, Arakawa, Hideki, Higuchi, Yoshinobu, Kanazawa, Keisuke, Okumura, Yoshiki
• Granted Patent: US 7,096,406 B2
• Time in Patent Office: Days
• US Class Current: 714/766
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate

Abstract

A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.

Claims

1. A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2ⁿ, where n is an integer greater than or equal to 2) cell memory via a data bus the width of which is a plurality of bits, and the memory controller comprising:

first through Mth ECC circuits, into which first through Mth (where M is greater than or equal to n) data groups of a first data bus connected to said host are input in parallel respectively, and which, for the first through Mth data groups, generate first through Mth error correction codes enabling correction of single-bit defect; and

,

data output unit, which outputs the data groups to a second data bus connected to data input/output terminals of said N-level cell memory such that the n data bits associated with a single N-level cell are separated into the first through Mth data groups, without overlap; and

wherein

said data output unit further outputs to said second data bus the respective error correction codes generated by said ECC circuits.

2. The memory controller for a multilevel cell memory according to claim 1, wherein the data input/output terminals of said N-level cell memory are divided, in order from the lowest, into first, second, . . . , Mth data groups, and said data output unit outputs data to the second data bus so as to be allocated, in order from the lowest, to the first, second, . . . , Mth data groups.

3. The memory controller for a multilevel cell memory according to claim 2, wherein the data of said first data bus is divided, in order from the lowest, into first, second, . . . , Mth data groups, and input to first through Mth ECC circuits.

4. The memory controller for a multilevel cell memory according to claim 1, wherein the data input/output terminals of said N-level cell memory are divided, in order from the lowest, into data groups associated with N-level cells, and said data output unit outputs data to the second data bus such that the data of the first, second, . . . , Mth data groups is cyclically repeated, in order from the lowest.

5. The memory controller for a multilevel cell memory according to claim 1, wherein, when reading data from said N-level cell memory, said first through Mth ECC circuits input the first through Mth data groups and first through Mth error correction codes transferred via said second data bus, and the first through Mth ECC circuits perform one-bit error correction within the first through Mth data groups.

6. The memory controller for a multilevel cell memory according to claim 5, wherein writing of data and ECC codes to said N-level cell memory is performed along the route, between said host and N-level cell memory, from the first data bus to the first through Mth ECC circuits, data output unit, and second data bus;

and data reading is performed along the opposite route.

7. The memory controller for a multilevel cell memory according to claim 1, wherein, upon writing to said multilevel cell memory, in synchronization with a clock, data is supplied from said first data bus, said data output unit outputs the data to said second data bus, and said ECC circuits generate error correction codes for each group;

and, after output of one page of data to said second data bus, said data output unit outputs said error correction codes to said second data bus, in synchronization with the clock.

8. The memory controller for a multilevel cell memory according to claim 1, wherein, upon reading from said multilevel cell memory, in synchronization with a clock, data is supplied from said second data bus, and said ECC circuits generate error correction codes for each data group;

and, after supply of one page worth of data, error correction codes are supplied from said second data bus, and said ECC circuits compare said generated error correction codes and the supplied error correction codes, and perform error detection and correction, in synchronization with the clock.

9. The memory controller for a multilevel cell memory according to claim 1, wherein said error correction codes have parity bits for a first group and for a second group respectively, where each digit of the bit number assigned to each data group is “

0”

for the first group and “

1”

for the second group.

10. The memory controller for a multilevel cell memory according to claim 9, wherein, during error detection and correction, if one of the pair of parity bits is coincident and the other is not coincident in all bit number digits, said ECC circuits detect the occurrence of a one-bit error.

11. The memory controller for a multilevel cell memory according to claim 10, wherein, during error detection and correction, said ECC circuits perform exclusive OR operations of supplied error correction codes, supplied from said memory, and error correction codes generated for data supplied from said memory, and, if one of the pair of parity bits is coincident and the other is not coincident in all bit number digits, the exclusive OR operation value of said odd-numbered bit number or even-numbered bit number is taken to be the bit number of error occurrence.

12. A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2ⁿ, where n is an integer greater than or equal to 2) cell memory, via data buses each with a plurality of bits, comprising:

a common ECC circuit, which receives, in order, first through Mth (where M is greater than or equal to n) data groups, separated in the address direction, for the data groups of a first data bus connected to said host, and generates first through Mth error correction codes capable of correction of single-bit defect for the respective first through Mth data groups;

error correction code holding unit, which holds said first through (M−

1)th error correction codes; and

,

data output unit, which outputs the data to a second data bus connected to said N-level cell memory, such that the n data bits associated with one N-level cell are separated into first through Mth data groups, without overlap; and

wherein

said data output unit outputs to said second data bus the first through (M−

1)th error correction codes held by said error correction code holding unit, and the Mth error correction code generated by said ECC circuit.

13. The memory controller for a multilevel cell memory according to claim 12, wherein, upon writing to said multilevel cell memory, in synchronization with a clock, data is supplied from said first data bus, said data output unit outputs the data to said second data bus, and said ECC circuit generates error correction codes in sequence for each data group;

and, after output of one page worth of data to said second data bus, said data output unit outputs said error correction codes to said second data bus, in synchronization with the clock.

14. The memory controller for a multilevel cell memory according to claim 12, wherein, upon reading from said multilevel cell memory, in synchronization with a clock, data is supplied from said second data bus, and said ECC circuit generates error correction codes in sequence for each data group;

and, after supply of one page of data, error correction codes are supplied from said second data bus, and said ECC circuit compares said generated error correction codes and the supplied error correction codes, and perform error detection and correction, in synchronization with the clock.

15. The memory controller for a multilevel cell memory according to claim 12, wherein said error correction codes have parity bits for a first group and for a second group respectively, where each digit of the bit number assigned to each data group is “

0”

for the first group and “

1”

for the second group.

16. A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2ⁿ, where n is an integer greater than or equal to 2) cell memory, via data buses each with a plurality of bits, comprising:

first through Mth ECC circuits, which receive first through Mth (where M is greater than or equal to n) data groups, separated in the address direction, for the data groups of a first data bus connected to said host, and generate first through Mth error correction codes capable of correction of single-bit defect for the respective first through Mth data groups; and

,

data output unit, which outputs the data to a second data bus connected to said N-level cell memory, such that the n data bits associated with one N-level cell are separated into first through Mth data groups, without overlap; and

wherein

said data output unit further outputs to said second data bus the respective error correction codes generated by said ECC circuits.

17. The memory controller for a multilevel cell memory according to claim 16, wherein, upon writing to said multilevel cell memory, in synchronization with a clock, data is supplied from said first data bus, said data output unit outputs the data to said second data bus, and said ECC circuits generate error correction codes for each group;

and, after output of one page worth of data to said second data bus, said data output unit outputs said error correction codes to said second data bus, in synchronization with the clock.

18. The memory controller for a multilevel cell memory according to claim 16, wherein, upon reading from said multilevel cell memory, in synchronization with a clock, data is supplied from said second data bus, and said ECC circuits generate error correction codes for each data group;

and, after supply of one page worth of data, error correction codes are supplied from said second data bus, and said ECC circuits compare said generated error correction codes and the supplied error correction codes, and perform error detection and correction, in synchronization with the clock.

19. The memory controller for a multilevel cell memory according to claim 16, wherein said error correction codes have parity bits for a first group and for a second group respectively, where each digit of the bit number assigned to each data group is “

0”

for the first group and “

1”

for the second group.