Memory controller for multilevel cell memory
First Claim
1. A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2n, where n is an integer greater than or equal to 2) cell memory via a data bus the width of which is a plurality of bits, and the memory controller comprising:
- first through Mth ECC circuits, into which first through Mth (where M is greater than or equal to n) data groups of a first data bus connected to said host are input in parallel respectively, and which, for the first through Mth data groups, generate first through Mth error correction codes enabling correction of single-bit defect; and
, data output unit, which outputs the data groups to a second data bus connected to data input/output terminals of said N-level cell memory such that the n data bits associated with a single N-level cell are separated into the first through Mth data groups, without overlap; and
wherein said data output unit further outputs to said second data bus the respective error correction codes generated by said ECC circuits.
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Abstract
A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.
176 Citations
19 Claims
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1. A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2n, where n is an integer greater than or equal to 2) cell memory via a data bus the width of which is a plurality of bits, and the memory controller comprising:
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first through Mth ECC circuits, into which first through Mth (where M is greater than or equal to n) data groups of a first data bus connected to said host are input in parallel respectively, and which, for the first through Mth data groups, generate first through Mth error correction codes enabling correction of single-bit defect; and
,data output unit, which outputs the data groups to a second data bus connected to data input/output terminals of said N-level cell memory such that the n data bits associated with a single N-level cell are separated into the first through Mth data groups, without overlap; and
whereinsaid data output unit further outputs to said second data bus the respective error correction codes generated by said ECC circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2n, where n is an integer greater than or equal to 2) cell memory, via data buses each with a plurality of bits, comprising:
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a common ECC circuit, which receives, in order, first through Mth (where M is greater than or equal to n) data groups, separated in the address direction, for the data groups of a first data bus connected to said host, and generates first through Mth error correction codes capable of correction of single-bit defect for the respective first through Mth data groups;
error correction code holding unit, which holds said first through (M−
1)th error correction codes; and
,data output unit, which outputs the data to a second data bus connected to said N-level cell memory, such that the n data bits associated with one N-level cell are separated into first through Mth data groups, without overlap; and
whereinsaid data output unit outputs to said second data bus the first through (M−
1)th error correction codes held by said error correction code holding unit, and the Mth error correction code generated by said ECC circuit. - View Dependent Claims (13, 14, 15)
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16. A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2n, where n is an integer greater than or equal to 2) cell memory, via data buses each with a plurality of bits, comprising:
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first through Mth ECC circuits, which receive first through Mth (where M is greater than or equal to n) data groups, separated in the address direction, for the data groups of a first data bus connected to said host, and generate first through Mth error correction codes capable of correction of single-bit defect for the respective first through Mth data groups; and
,data output unit, which outputs the data to a second data bus connected to said N-level cell memory, such that the n data bits associated with one N-level cell are separated into first through Mth data groups, without overlap; and
whereinsaid data output unit further outputs to said second data bus the respective error correction codes generated by said ECC circuits. - View Dependent Claims (17, 18, 19)
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Specification