Wide band digital phase locked loop (PLL) with a half-frequency output

• US 20030041667A1
• Filed: 08/22/2001
• Published: 03/06/2003
• Est. Priority Date: 08/22/2001
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: White, Stanley A.
• Granted Patent: US 6,564,636 B2
• Time in Patent Office: Days
• US Class Current: 73/504.12
• CPC Class Codes: E05Y 2400/30 of motors
• CPC Class Codes: G01C 19/56 Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
• CPC Class Codes: G01C 21/188 for accumulated errors, e.g. by coupling inertial systems with absolute positioning systems
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H04L 27/1525 using quadrature demodulation

Abstract

A digital phase locked loop includes an automatic gain control that applies a gain to an input signal in order to provide a gain controlled signal. A 90 ° phase shifter applies a 90 ° phase shift to the gain controlled signal in order to provide a 90 ° phase shifted version of the gain controlled signal. A phase detector is driven by the gain controlled signal, by the 90 ° phase shifted version of the gain controlled signal, and by sinusoidal and co-sinusoidal signals. A loop filter integrates an output of the phase detector and provide servo equalization for the phase-locked loop. A digital dual frequency oscillator has a fundamental frequency controlled by an output signal from the loop filter. Also, the digital dual frequency oscillator generates the sinusoidal and co-sinusoidal signals.

Claims

1. An apparatus implementing a digital phase locked loop comprising:

an automatic gain control arranged to apply gain to an input signal in order to produce a gain controlled signal;

a 90°

phase shifter arranged to provide a 90°

phase shifted version of the gain controlled signal;

a phase detector driven by the gain controlled signal, by the 90°

phase shifted version of the gain controlled signal, and by sinusoidal and co-sinusoidal signals;

a loop filter arranged to integrate an output of the phase detector and to provide servo equalization for the phase-locked loop; and

,

a digital dual frequency oscillator having a fundamental frequency controlled by an output signal from the loop filter in order to generate the sinusoidal and co-sinusoidal signals.

2. The apparatus of claim 1 wherein the automatic gain control includes an error generator that generates an AGC error based upon the gain controlled signal, the 90°

phase shifted version of the gain controlled signal, and a constant.

3. The apparatus of claim 2 wherein the error generator is arranged to generate the AGC error by subtracting squares of the gain controlled signal and the 90°

phase shifted version of the gain controlled signal from the constant.

4. The apparatus of claim 3 wherein the constant is substantially 1.0.

5. The apparatus of claim 2 wherein the AGC error is scaled and drives an accumulator loop that contains a limiter.

6. The apparatus of claim 5 wherein the accumulator output drives a multiplier, and wherein the multiplier functions as an AGC amplifier operating on the input signal.

7. The apparatus of claim 2 wherein the 90°

phase shifter comprises an adaptively gain-adjusted single-sample-time delay Hilbert transformer.

8. The apparatus of claim 7 wherein the AGC error is scaled and drives an accumulator loop that contains a limiter.

9. The apparatus of claim 8 further comprising switches arranged to substantially eliminate interaction between the accumulator loop and the adaptively gain-adjusted single-sample-time delay Hilbert transformer.

10. The apparatus of claim 1 wherein the loop filter comprises an integrator, wherein the integrator comprises a feedback loop and a lead filter, and wherein the feedback loop comprises a limiter.

11. The apparatus of claim 1 wherein the digital dual frequency oscillator is arranged to produce in-phase and quadrature components of the output signal from the loop filter, wherein the digital dual frequency oscillator is arranged to produce squares of the in-phase and quadrature components, wherein the digital dual frequency oscillator is arranged to sum the squares of the in-phase and quadrature components so as to produce a measure of an amplitude of an output of the digital dual frequency oscillator, wherein the digital dual frequency oscillator has a response having poles, and wherein the amplitude of the output of the digital dual frequency oscillator is set to a desired level by moving the poles inside or outside of the unit circle in response to the sum of the squares.

12. The apparatus of claim 1 wherein the digital dual frequency oscillator is arranged to produce primary outputs, and wherein the primary outputs comprise in-phase and quadrature components at the fundamental frequency.

13. The apparatus of claim 12 wherein the digital dual frequency oscillator is arranged to produce secondary outputs, and wherein the secondary outputs comprise in-phase and quadrature components having a frequency that is twice the fundamental frequency.

14. The apparatus of claim 13 wherein the digital dual frequency oscillator implements trigonometric sine and cosine double-angle formulas to produce the secondary outputs.

15. The apparatus of claim 14 wherein the input signal has a frequency, and wherein the secondary outputs are coupled to the phase detector so as to force the fundamental frequency of the digital dual frequency oscillator to be one-half of the frequency of the input signal.

16. The apparatus of claim 1 wherein the 90°

phase shifter comprises two single-sample-period-delay elements.

17. The apparatus of claim 1 further comprising an amplitude controller arranged to control an amplitude of a signal generated by the digital dual frequency oscillator.

18. A method implemented by a phase locked loop comprising:

applying a gain to an input signal to produce an in-phase gain controlled signal, wherein the input signal has a frequency 2f₀;

shifting the in-phase gain controlled signal by 90°

to produce a quadrature gain controlled signal;

detecting a phase difference dependent upon the in-phase gain controlled signal, the quadrature gain controlled signal, and first and second output signals; and

,

producing the first and second output signals and a third output signal in response to the phase difference, wherein the third output signal has a frequency f₀, and wherein the each of the first and second output frequencies has a frequency 2f₀.

19. The method of claim 18 wherein the producing of the first and second output signals and a third output signal comprises:

integrating and servo equalizing the phase difference; and

,

producing the first and second output signals and the third output signal in response to the integrated and servo equalized phase difference.

20. The method of claim 18 wherein the applying of a gain to an input signal comprises:

generating an AGC error based on the in-phase gain controlled signal, the quadrature gain controlled signal, and a constant; and

,

applying the gain to the input signal based on the AGC error.

21. The method of claim 20 wherein the generating of an AGC error comprises:

squaring the in-phase gain controlled signal and the quadrature gain controlled signal; and

,

generating the AGC error by subtracting the squares of the in-phase gain controlled signal and the quadrature gain controlled signal from the constant.

22. The method of claim 21 wherein the constant is substantially 1.0.

23. The method of claim 20 wherein the applying of the gain comprises;

scaling the AGC error;

driving an accumulator loop that contains a limiter in response to the scaled AGC error; and

,

applying the gain to the input signal based on an output of the accumulator loop.

24. The method of claim 23 wherein the applying of the gain to the input signal comprises multiplying the input signal by the output of the accumulator loop.

25. The method of claim 18 wherein the shifting of the in-phase gain controlled signal by 90°

comprises applying an adaptively gain-adjusted single-sample-time delay Hilbert transform to the in-phase gain controlled signal.

26. The method of claim 25 wherein the applying of a gain to an input signal comprises:

generating an AGC error; and

,

applying the gain to the input signal based on the AGC error.

27. The method of claim 26 further comprising performing switching so as substantially eliminate interaction between the applying of the gain to the input signal based on the AGC error and the applying of the adaptively gain-adjusted single-sample-time delay Hilbert transform.

28. The method of claim 18 wherein one of the first and second output signals is based upon an in-phase component, wherein the other of the first and second output signals is based upon a quadrature component, wherein each of the in-phase and quadrature components has a frequency f₀, and wherein the producing of the first and second output signals comprises:

squaring the in-phase component;

squaring the quadrature component;

summing the squares of the in-phase and quadrature components so as produce a summed output, wherein the summed output has an amplitude; and

,

comparing the sum to a reference to produce an amplitude control signal; and

,

controlling the amplitude of at least one of the first, second, and third output signals in response to the amplitude control signal.

29. The method of claim 18 wherein the third output signal comprises in-phase and quadrature components.

30. The method of claim 18 wherein one of the first and second output signals is based upon an in-phase component, wherein the other of the first and second output signals is based upon a quadrature component, wherein each of the in-phase and quadrature components has a frequency f₀, and wherein the producing of the first and second output signals comprises:

multiplying the in-phase and quadrature components to produce a product and doubling the product so as to produce the first output signal in accordance with the following equation;

sin(2θ

)=2 sin(θ

) cos(θ

)

wherein sin(2θ

) is the first output signal, wherein sin(θ

) is the in-phase component, and wherein cos(θ

) is the quadrature component;

squaring the in-phase component;

squaring the quadrature component; and

,

subtracting the squared quadrature component from the squared in-phase component so as to produce the second output signal in accordance with the following equation;

cos(2θ

)=cos²(θ

)−

sin²(θ

)

wherein cos(2θ

) is the second output signal, wherein sin²(θ

) is the squared in-phase component, and wherein cos²(θ

) is the squared quadrature component.

31. The method of claim 18 wherein the detecting of a phase difference comprises:

multiplying the in-phase gain controlled signal by the first output signal to produce a first product;

multiplying the quadrature gain controlled signal by the second output signal to produce a second product; and

,

forming a difference between the first and second products.

32. A method of driving a gyro comprising:

shifting an in-phase signal by 90°

to produce a quadrature signal, wherein the in-phase signal is derived from a first output of the gyro, wherein the in-phase signal has a frequency 2f₀, and wherein the quadrature signal has a frequency 2f₀;

detecting a phase difference dependent upon the in-phase signal, the quadrature signal, and first and second output signals;

producing the first and second output signals and a third output signal in response to the phase difference, wherein the third output signal has a frequency f₀, and wherein the each of the first and second frequencies has a frequency 2f₀;

producing an angular rate indicating signal based upon a second output of the gyro and the first and second output signals; and

,

driving the gyro in response to the third output signal.

33. The method of claim 32 wherein the shifting of an in-phase signal by 90°

to produce a quadrature signal comprises;

applying a gain to an input signal to produce in-phase signal, wherein the input signal is derived from the first output of the gyro; and

,

shifting the in-phase signal by 90°

to produce the quadrature signal.

34. The method of claim 33 wherein the applying of a gain to an input signal comprises:

generating an AGC error based on the in-phase signal, the quadrature signal, and a constant; and

,

applying the gain to the input signal based on the AGC error.

35. The method of claim 33 wherein the shifting of the in-phase signal by 90°

comprises applying an adaptively gain-adjusted single-sample-time delay Hilbert transform to the in-phase signal.

36. The method of claim 35 wherein the applying of a gain to an input signal comprises:

generating an AGC error; and

,

applying the gain to the input signal based on the AGC error.

37. The method of claim 36 further comprising performing switching so as to substantially eliminate interaction between the applying of the gain to the input signal based on the AGC error and the applying of the adaptively gain-adjusted single-sample-time delay Hilbert transform.

38. The method of claim 32 wherein one of the first and second output signals is based upon an in-phase component, wherein the other of the first and second output signals is based upon a quadrature component, wherein each of the in-phase and quadrature components has a frequency f₀, and wherein the producing of the first and second output signals comprises:

multiplying the in-phase and quadrature components to produce a product and doubling the product so as to produce the first output signal in accordance with the following equation;

sin(2θ

)=2 sin(θ

) cos(θ

)

wherein sin(2θ

) is the first output signal, wherein sin(θ

) is the in-phase component, and wherein cos(θ

) is the quadrature component;

squaring the in-phase component;

squaring the quadrature component; and

,

subtracting the squared quadrature component from the squared in-phase component so as to produce the second output signal in accordance with the following equation;

cos(2θ

)=cos²(θ

)−

sin²(θ

)

wherein cos(2θ

) is the second output signal, wherein sin²(θ

) is the squared in-phase component, and wherein cos²(θ

) is the squared quadrature component.

39. The method of claim 32 wherein the detecting of a phase difference comprises:

multiplying the in-phase signal by the first output signal to produce a first product;

multiplying the quadrature signal by the second output signal to produce a second product; and

,

forming a difference between the first and second products.