Semiconductor device

• US 20030042537A1
• Filed: 09/10/2002
• Published: 03/06/2003
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakamura, Hideki, Nakamura, Katsumi, Kusunoki, Shigeru
• Granted Patent: US 6,953,968 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n⁻ silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n⁻ silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n⁻ silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n⁻ silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n⁻ silicon substrate (1).

Claims

1. A semiconductor device characterized by comprising:

an insulating gate type field effect transistor portion having a source region (3) and a drain region (1), which are opposed to each other sandwiching a channel formation region (2), as well as a gate electrode (5a), which is opposed to said channel formation region (2) sandwiching a gate insulating film (4, 4a); and

a stabilizing plate (5b), made of a conductor or of a semiconductor, which is opposed to said drain region (1) sandwiching an insulating film (4, 4b) for a plate and which forms, together with said drain region (1), a capacitor, characterized in that

a stabilizing plate capacitor formed between said stabilizing plate (5b) and said drain region (1) has a capacitance greater than that of a gate-drain capacitor formed between said gate electrode (5a) and said drain region (1).

2. The semiconductor device according to claim 1, characterized in that said stabilizing plate (5b) is electrically connected to said source region (3).

3. The semiconductor device according to claim 1, characterized in that said stabilizing plate (5b) forms, together with the source potential, a capacitor.

4. The semiconductor device according to claim 1, characterized in that the film thickness of said insulating film (4b) for a plate in a portion where said stabilizing plate (5b) is opposed to said drain region (1) is thinner than the film thickness of said gate insulating film (4a) in a portion where said gate electrode (5a) is opposed to said drain region (1).

5. The semiconductor device according to claim 1, characterized in that the dielectric constant of said insulating film (4b) for a plate in a portion where said stabilizing plate (5b) is opposed to said drain region (1) is greater than the dielectric constant of said gate insulating film (4a) in a portion where said gate electrode (5a) is opposed to said drain region (1).

6. The semiconductor device according to claim 1, characterized in that the area where said stabilizing plate (5b) is opposed to said drain region (1) is greater than the area where said gate electrode (5a) is opposed to said drain region (1).

7. The semiconductor device according to claim 1, characterized in that the impurity concentration of said drain region (1) in a portion opposed to said stabilizing plate (5b) is higher than the impurity concentration of said drain region (1) in a portion opposed to said gate electrode (5a).

8. The semiconductor device according to claim 1, characterized in that

a plurality of transistors of the same type as said insulating gate type field effect transistor is arranged side by side, and

two or more plates of the same type as said stabilizing plate (5b) are arranged in a region sandwiched by two of said insulating gate type field effect transistors.

9. The semiconductor device according to claim 8, characterized in that the impurity concentration of a region in said drain region (1) sandwiched by said two or more stabilizing plates (5b) is higher than the impurity concentration of the other regions in said drain region (1).

10. The semiconductor device according to claim 6, characterized in that

said channel formation region (2) is within a body region of a conductive type that is opposite to that of said source region (3) and said drain region (1), and

the ratio of the length where said drain region (1) is opposed to said stabilizing plate (5b) to the length where said body region (2) is opposed to said stabilizing plate (5b) is greater than the ration of the length where said drain region (1) is opposed to said gate electrode (5a) to the length where said body region (2) is opposed to said gate electrode (5a).

11. The semiconductor device according to claim 1, characterized by further comprising a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and having a trench (4a) for a gate formed on said first main surface,

wherein said gate electrode (5a) fills in said trench (4a) for a gate.

12. The semiconductor device according to claim 11, characterized in that said gate electrode (5a) has two sides opposed to each other and is opposed to said channel formation region (2) in each of said two sides.

13. The semiconductor device according to claim 1, characterized in that an electrode (11) on the source side and an electrode (12) on the drain side are both formed in the first main surface of said semiconductor substrate.

14. The semiconductor device according to claim 1, characterized in that an electrode (11) on the source side is formed in the first main surface of said semiconductor substrate and an electrode (12) on the drain side is formed in the second main surface of said semiconductor substrate.

15. The semiconductor device according to claim 11, characterized in that said trench (4a) for a gate reaches to said drain region (1).

16. The semiconductor device according to claim 1, characterized in that a plurality of cells each of which includes said insulating gate type field effect transistor portion are arranged side by side and said stabilizing plate (5b) is arranged in a terminal portion of said arranged plurality of cells.

17. The semiconductor device according to claim 16, characterized in that a plurality of plates of the same type as said stabilizing plate (5b) are arranged in the terminal portion of said arranged plurality of cells.

27. (added) The semiconductor device according to claim 1, characterized in that said channel formation region (2) and said stabilizing plate (5b) exist within a region sandwiched between two adjacent gate electrodes (5a).

18. A semiconductor device, characterized by comprising:

a semiconductor substrate having a first main surface and a second main surface which are opposed to each other;

first and second insulating gate type field effect transistor portions respectively having source regions (3) and drain regions (1), which are opposed to each other sandwiching channel formation regions (2), and gate electrodes (5a) which are opposed to said channel formation regions (2) sandwiching gate insulating films (4a);

a first stabilizing plate (5b), made of a conductor or of a semiconductor, which is opposed to said drain region (1) of said first insulating gate type field effect transistor portion sandwiching a first insulating film (4b) for a plate and that forms, together with said drain region (1) of said first insulating gate type field effect transistor portion, a capacitor; and

a second stabilizing plate (5b), made of a conductor or of a semiconductor, which is opposed to said drain region (1) of said second insulating gate type field effect transistor portion sandwiching a second insulating film (4b) for a plate and that forms, together with said drain region (1) of said second insulating gate type field effect transistor portion, a capacitor,

wherein said first insulating gate type field effect transistor portion is formed on said first main surface while said second insulating gate type field effect transistor portion is formed in said second main surface and a current is allowed to flow between said first and second insulating gate type field effect transistor portions.

19. The semiconductor device according to claim 18, characterized in that

a first stabilizing plate capacitor formed between said first stabilizing plate (5b) and said drain region (1) of said first insulating gate type field effect transistor portion has a capacitance greater than that of a first gate-drain capacitor formed between said gate electrode (5a) and said drain region (1) of said first insulating gate type field effect transistor portion, and

a second stabilizing plate capacitor formed between said second stabilizing plate (5b) and said drain region (1) of said second insulating gate type field effect transistor portion has a capacitance greater than that of a second gate-drain capacitor formed between said gate electrode (5a) and said drain region (1) of said second insulating gate type field effect transistor portion.

20. The semiconductor device according to claim 18, characterized in that

a plurality of transistors of the same type as said first insulating gate type field effect transistor is arranged side by side and two or more plates of the same type as said first stabilizing plate (5b) are arranged in a region sandwiched between two of said first insulating gate type field effect transistors,

a plurality of transistors of the same type as said second insulating gate type field effect transistor is arranged side by side and two or more plates of the same type as said second stabilizing plate (5b) are arranged in a region sandwiched between two of said second insulating gate type field effect transistors and in that

the impurity concentration of a region in said drain region (1) sandwiched between said two or more first stabilizing plates (5b) and the impurity concentration of a region in said drain region (1) sandwiched between said two or more second stabilizing plates (5b) are higher than the impurity concentration of the other regions in said drain region (1).

21. The semiconductor device according to claim 18, characterized in that

said semiconductor substrate has a first trench (4a) for a gate created in said first main surface and a second trench (4a) for a gate created in said second main surface,

said gate electrode (5a) of said first insulating gate type field effect transistor portion fills in said first trench (4a) for a gate and

said gate electrode (5a) of said second insulating gate type field effect transistor portion fills in said second trench (4a) for a gate.

22. The semiconductor device according to claim 21, characterized in that

said gate electrode (5a) of said first insulating gate type field effect transistor portion has two sides opposed to each other and is opposed to said channel formation region (2) of said first insulating gate type field effect transistor portion in each of said two sides and

said gate electrode (5a) of said second insulating gate type field effect transistor portion has two sides opposed to each other and is opposed to said channel formation region (2) of said second insulating gate type field effect transistor portion in each of said two sides.

23. The semiconductor device according to claim 18, characterized in that a plurality of cells each of which includes said first and second insulating gate type field effect transistor portions are arranged side by side and said first and second stabilizing plate (5b) are arranged in a terminal portion of said arranged plurality of cells.

24. The semiconductor device according to claim 18, characterized in that a plurality of plates of the same type as said first stabilizing plate (5b) and a plurality of plates of the same type as said second stabilizing plate (5b) are arranged in terminal portions of said arranged plurality of cells.

25. A semiconductor device comprising:

an insulating gate type field effect transistor portion having a source region (3) and a drain region (1), which are opposed to each other sandwiching a channel formation region (2), as well as a gate electrode (5a) that is opposed to said channel formation region (2) sandwiching a gate insulating film (4a); and

a stabilizing plate (5b) made of a conductor or a semiconductor, which is opposed to said drain region (1) sandwiching an insulating film (4b) for a plate and which forms, together with said drain region (1), a capacitor,

wherein a plurality of cells each of which includes said insulating gate type field effect transistor portion is arranged side by side and said stabilizing plate (5b) is arranged in a terminal portion of said arranged plurality of cells.

26. The semiconductor device according to claim 25, characterized in that a plurality of plates of the same type as said stabilizing plate (5b) is arranged in the terminal portion of said arranged plurality of cells.