Silicon carbide power device having protective diode and method for manufacturing silicon carbide power device having protective diode

• US 20030042538A1
• Filed: 08/29/2002
• Published: 03/06/2003
• Est. Priority Date: 08/29/2001
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Yamamoto, Tsuyoshi, Morishita, Toshiyuki, Nakamura, Hiroki, Kumar, Rajesh
• Granted Patent: US 6,855,981 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66992 controllable only by the variation of applied heat controllable by IR radiation H01L31/00; measuring quantity of heat G01K17/00
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A silicon carbide power device includes a junction field effect transistor and a protective diode, which is a Zener or PN junction diode. The PN junction of the protective diode has a breakdown voltage lower than the PN junction of the transistor. Another silicon carbide power device includes a protective diode, which is a Schottky diode. The Schottky diode has a breakdown voltage lower than the PN junction of the transistor by adjusting Schottky barrier height or the depletion layer formed in the semiconductor included in the Schottky diode. Another silicon carbide power device includes three protective diodes, which are Zener diodes. Two of the protective diodes are used to clamp the voltages applied to the gate and the drain of the transistor due to surge energy and used to release the surge energy. The last diode is a thermo-sensitive diode, with which the temperature of the JFET is measured.

Claims

1. A silicon carbide power device comprising:

a silicon carbide power transistor; and

a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor.

2. The device in claim 1, wherein the silicon carbide power transistor is a junction field effect transistor.

3. The device in claim 2 including:

a substrate, which is substantially made of SiC and has a first conduction type;

a drift layer, which is substantially made of SiC and has the first conduction type;

a first JFET impurity layer, which is substantially made of SiC and has a second conduction type;

a source layer, which is substantially made of SiC and has the first conduction type, wherein the drift layer has a impurity concentration lower than those of the substrate and the source layer, wherein the drift layer, the first JFET impurity layer, and the source layer are sequentially layered in this order on a surface of the substrate, and wherein the junction field effect transistor includes;

a part of the substrate;

a part of the drift layer;

a part of the first JFET impurity layer;

a part of the source layer, wherein a trench extends from a surface of the part of the source layer to the part of the drift layer through the part of the first JFET impurity layer;

a channel layer, which is substantially made of SiC, has the first conduction type, and is located on a surface defining the trench; and

a second JFET impurity layer, which is substantially made of SiC, has the second conduction type, and located on the channel layer.

4. The device in claim 3, wherein the first JFET impurity layer and the second JFET impurity layer make up a gate of the transistor.

5. The device in claim 3, wherein the first JFET impurity layer makes up a gate of the device, and the second JFET impurity layer is electrically connected to the source layer and is closer to the substrate than the first JFET impurity layer.

6. The device in claim 3, wherein the protective diode is a Zener or PN junction diode, which has a PN junction, and an electrode of the protective diode is grounded.

7. The device in claim 6, wherein the PN junction of the protective diode has a breakdown voltage lower than that of a PN junction formed with the first JFET impurity layer and the drift layer in the transistor.

8. The device in claim 3, wherein the protective diode is a Schottky diode and an electrode of the protective diode is grounded.

9. The device in claim 8, wherein a Schottky junction of the Schottky diode has a breakdown voltage lower than that of a PN junction formed with the first JFET impurity layer and the drift layer in the transistor.

10. The device in claim 9, wherein the Schottky diode includes an electrode that substantially determines the breakdown voltage of the diode using a Schottky barrier height.

11. The device in claim 9, wherein the Schottky diode includes a part of the substrate and a part of the drift layer, wherein the breakdown voltage of the diode is determined by the distance between the boundary of the Schottky junction and the boundary between the part of the drift layer and the part of the substrate.

12. The device in claim 3, wherein the protective diode accounts for 10 to 50% of the entire area of the device.

13. The device in claim 6, wherein the protective diode includes:

a part of the substrate;

a part of the drift layer, wherein a trench extends from a surface of a part of the source layer to the part of the drift layer through a part of the first JFET impurity layer;

an impurity layer, which is substantially made of SiC, has the second conduction type, and located on a surface defining the trench of the protective diode; and

an electrode, which is located on the impurity layer and is grounded, wherein the impurity layer of the protective diode is closer to the substrate than the second JFET impurity layer in the transistor is.

14. The device in claim 6, wherein the protective diode includes:

a part of the substrate;

a part of the drift layer, wherein a trench, the depth of which is substantially equal to that of the trench in the transistor, extends from a surface of a part of the source layer to the part of the drift layer through a part of the first JFET impurity layer;

a first diode impurity layer, which is substantially made of SiC, has the first conduction type, and located on a surface defining the trench of the protective diode;

a second diode impurity layer, which is substantially made of SiC, has the second conduction type, and located on the first diode impurity layer; and

an electrode, which is located on the second diode impurity layer and is grounded, wherein the second diode impurity layer of the protective diode is closer to the substrate than the second JFET impurity layer in the transistor is.

15. The device in claim 6, wherein the protective diode includes:

a part of the substrate;

a part of the drift layer;

a region, which is substantially made of SiC, has the second conduction type, and is located in a surface of the drift layer;

a part of the first JFET impurity layer; and

an electrode, which is in ohmic contact with the part of the first JFET impurity layer and is grounded, wherein the region is closer to the substrate than the second JFET impurity layer in the transistor is.

16. The device in claim 6, wherein the protective diode includes:

a part of the substrate;

a part of the drift layer, wherein a trench deeper than the trench in the transistor extends from a surface of a part of the source layer to the part of the drift layer through a part of the first JFET impurity layer;

a first diode impurity layer, which is substantially made of SiC, has the first conduction type, and located on a surface defining the trench in the protective diode;

a second diode impurity layer, which is substantially made of SiC, has the second conduction type, and located on the first impurity; and

an electrode, which is located on the second diode impurity layer and is grounded, wherein the second diode impurity layer of the protective diode is closer to the substrate than the second JFET impurity layer in the transistor is.

17. The device in claim 8, wherein the protective diode includes:

a part of the substrate;

a part of the drift layer, wherein a trench extends from a surface of a part of the source layer to the part of the drift layer through a part of the first JFET impurity layer;

an impurity layer, which is substantially made of SiC, has the first conduction type, and located on a surface defining the trench of the protective diode; and

an electrode, which is in electric contact with the impurity layer to form a Schottky junction and is grounded, wherein the protective diode has a breakdown voltage lower than that a PN junction formed with the first JFET impurity layer and the drift layer in the transistor.

18. The device in claim 1, wherein the protective diode is substantially made of polycrystalline silicon.

19. The device in claim 1, wherein the protective diode is substantially made of SiC.

20. The device in claim 1 including a JTE member at a periphery of the device, wherein the protective diode is located above the JTE member.

21. The device in claim 20 including a conductive layer, which is located between the protective diode and the JTE member.

22. The device in claim 1 including an insulating layer, on which the protective diode is located.

23. The device in claim 1 including:

an equivalent potential ring; and

a gate terminal, wherein the silicon carbide power transistor includes a drain and a gate, wherein the equivalent potential ring has the same potential as the drain, wherein a first end of the protective diode is electrically connected to the equivalent potential ring, and wherein a second end of the protective diode is electrically connected to the gate terminal, which has the same potential as the gate.

24. The device in claim 1 including:

a drift layer, which is substantially made of SiC and has the first conduction type; and

a first JFET impurity layer, which is substantially made of SiC and has a second conduction type, which is located on the drift layer, wherein the diode is thermo-sensitive for measuring the temperature of the silicon carbide power transistor and electrically separated from the drift layer by the first JFET impurity layer.

25. A method for manufacturing a silicon carbide power device including a junction field effect transistor and a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor, the method comprising steps of:

forming a first epitaxial layer, which is substantially made of SiC and has a first conduction type, a second epitaxial layer, which is substantially made of SiC and has a second conduction type, and a third epitaxial layer, which is substantially made of SiC and has the first conduction type, in this order on a substrate, which is substantially made of SiC and has the first conduction type, by epitaxial growth;

forming simultaneously a first trench and a second trench by etching such that the first and second trenches extend from a surface of the third epitaxial layer to the first epitaxial layer through the second epitaxial layer and have substantially the same depth;

forming a channel layer, which is substantially made of SiC, has the first conduction type, on a surface defining the first trench;

forming a second JFET impurity layer, which is substantially made of SiC, has the second conduction type, on the channel layer;

forming an impurity layer, which is substantially made of SiC and has the second conduction type, on a surface defining the second trench; and

forming an electrode on the impurity layer.

26. A method for manufacturing a silicon carbide power device including a junction field effect transistor and a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor, the method comprising steps of:

forming a first epitaxial layer, which is substantially made of SiC and has a first conduction type, a second epitaxial layer, which is substantially made of SiC and has a second conduction type, and a third epitaxial layer, which is substantially made of SiC and has the first conduction type, in this order on a substrate, which is substantially made of SiC and has the first conduction type, by epitaxial growth;

forming simultaneously a first trench and a second trench by etching such that the first and second trenches extend from a surface of the third epitaxial layer to the first epitaxial layer through the second epitaxial layer and have substantially the same depth;

forming a channel layer, which is substantially made of SiC, has the first conduction type, on a surface defining the first trench;

forming a second JFET impurity layer, which is substantially made of SiC, has the second conduction type, on the channel layer;

forming a first diode impurity layer, which is substantially made of SiC and has the first conduction type, on a surface defining the second trench such that the first diode impurity layer is thinner than the channel layer;

forming a second diode impurity layer, which is substantially made of SiC and has the second conduction type; and

forming an electrode on the second diode impurity layer.

27. A method for manufacturing a silicon carbide power device including a junction field effect transistor and a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor, the method comprising steps of:

forming a first epitaxial layer, which is substantially made of SiC and has a first conduction type, on a substrate, which is substantially made of SiC and has the first conduction type, by epitaxial growth;

forming a region, which is substantially made of SiC and has a second conduction type, in a surface of the first epitaxial layer by ion implantation;

forming a second epitaxial layer, which is substantially made of SiC and has the second conduction type, and a third epitaxial layer, which is substantially made of SiC and has the first conduction type, in this order on the first epitaxial layer by epitaxial growth;

forming a trench by etching such that the trench extends from a surface of the third epitaxial layer to the first epitaxial layer through the second epitaxial layer;

forming a channel layer, which is substantially made of SiC, has the first conduction type, on a surface defining the first trench;

forming a second JFET impurity layer, which is substantially made of SiC, has the second conduction type, on the channel layer, wherein a depth of region, a depth of the trench, and a thickness of the channel layer are determined such that the region is closer to the substrate than the second JFET impurity layer is; and

forming an electrode such that the electrode is in ohmic contact with the third epitaxial layer.

28. A method for manufacturing a silicon carbide power device including a junction field effect transistor and a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor, the method comprising steps of:

forming a first epitaxial layer, which is substantially made of SiC and has a first conduction type, a second epitaxial layer, which is substantially made of SiC and has a second conduction type, and a third epitaxial layer, which is substantially made of SiC and has the first conduction type, in this order on a substrate, which is substantially made of SiC and has the first conduction type, by epitaxial growth;

forming a first trench by etching such that the first trench extends from a surface of the third epitaxial layer to the first epitaxial layer through the second epitaxial layer;

forming a second trench deeper than the first trench by etching such that the second trench extends from the surface of the third epitaxial layer to the first epitaxial layer through the second epitaxial layer;

forming a channel layer, which is substantially made of SiC, has the first conduction type, on a surface defining the first trench;

forming a second JFET impurity layer, which is substantially made of SiC, has the second conduction type, on the channel layer;

forming a first diode impurity layer, which is substantially made of SiC and has the first conduction type, on a surface defining the second trench;

forming a second diode impurity layer, which is substantially made of SiC and has the second conduction type, wherein a depth of the first trench, a depth of the second trench, a thickness of the channel layer, and a thickness of the first diode impurity layer are determined such that the second diode impurity layer is closer to the substrate than the second JFET impurity layer is; and

forming an electrode on the second diode impurity layer.

29. A method for manufacturing a silicon carbide power device including a junction field effect transistor and a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor, the method comprising steps of:

forming a first epitaxial layer, which is substantially made of SiC and has a first conduction type, a second epitaxial layer, which is substantially made of SiC and has a second conduction type, and a third epitaxial layer, which is substantially made of SiC and has the first conduction type, in this order on a substrate, which is substantially made of SiC and has the first conduction type, by epitaxial growth;

forming simultaneously a first trench and a second trench by etching such that the first trench and second trenches extends from a surface of the third epitaxial layer to the first epitaxial layer through the second epitaxial layer;

forming a channel layer, which is substantially made of SiC, has the first conduction type, on a surface defining the first trench;

forming a second JFET impurity layer, which is substantially made of SiC, has the second conduction type, on the channel layer;

forming an impurity layer, which is substantially made of SiC and has the first conduction type, on a surface defining the second trench; and

forming an electrode on the impurity layer to make a Schottky junction with the impurity layer.

30. A method for manufacturing a silicon carbide power device including a junction field effect transistor and a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor, the method comprising a step of forming the protective diode from a polycrystalline silicon film after a step having a treatment temperature higher than 1200°

C. are completed to avoid undesired sublimation of silicon from the diode and undesired outward diffusion of implanted ions in the diode.

31. A method for manufacturing a silicon carbide power device including a junction field effect transistor and a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor, the method comprising a step of:

forming the protective diode from a polycrystalline silicon film;

forming an ohmic contact electrode for the transistor; and

forming an ohmic contact electrode for the protective diode after the step of forming the ohmic contact electrode for the transistor to avoid undesired diffusion of a material of the ohmic contact electrodes for the protective diode into the protective diode.

32. The method in claim 31, wherein the ohmic contact electrode for the protective diode simultaneously gets electrically connected to the ohmic contact electrode for the transistor at the step of forming the ohmic contact electrode for the protective diode.

33. A method for manufacturing a silicon carbide power device including a junction field effect transistor and a protective diode, which prevents the transistor from being destroyed and protects a circuit that controls a gate of the transistor, the method comprising steps of:

forming a first epitaxial layer, which is substantially made of SiC and has a first conduction type, on a substrate, which is substantially made of SiC and has the first conduction type;

forming a second epitaxial layer, which is substantially made of SiC and has a second conduction type, on the first epitaxial layer;

forming a third epitaxial layer, which is substantially made of SiC and has the first conduction type, on the second epitaxial layer, wherein the first epitaxial layer is formed to have a impurity concentration lower than those of the substrate and the third epitaxial layer;

forming a trench that extends from a surface of the third epitaxial layer to the first epitaxial layer through the second epitaxial layer;

forming a fourth epitaxial layer, which is substantially made of SiC and has the first conduction type, on a surface defining the trench;

filling the rest of the trench with a fifth epitaxial layer, which is substantially made of SiC and has the second conduction type;

planarizing the fourth and fifth epitaxial layers using CMP to a level defined by an upper surface of the third epitaxial layer such that the upper surface of the third epitaxial layer is exposed and an upper surface of the fifth epitaxial layer is substantially at the same level as the upper surface of the third epitaxial layer to form a channel layer and a second JFET impurity layer from the fourth and fifth epitaxial layers, respectively;

forming a substantially flat ohmic contact electrode, which electrically connects the second JFET impurity layer and the third epitaxial layer; and

connecting electrically the second epitaxial layer to a gate terminal of the device, wherein the trench and the fourth and fifth epitaxial layers are formed such that the second JFET impurity layer is closer to the substrate than the second epitaxial layer is.