Nonvolatile semiconductor memory device having erasing characteristic improved

• US 20030042558A1
• Filed: 08/29/2002
• Published: 03/06/2003
• Est. Priority Date: 08/31/2001
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Masayuki, Goda, Akira, Noguchi, Mitsuhiro, Saida, Shigehiko
• Application Number:
  US10/230,092
• Publication Number:
  US 20030042558A1
• Time in Patent Office: Days
• US Class Current: 257/406
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A memory cell which allows information to be written or erased electrically. The memory cell includes a gate insulation film including three layers, i.e., a first insulation layer, an electric charge accumulating layer and a second insulation layer and a gate electrode formed on the gate insulation film. The electric charge accumulating layer is composed of a silicon nitride film or silicon oxynitride film. The first and second insulation layers are composed of a silicon oxide film or silicon oxynitride film containing more oxygen composition than the electric charge accumulating layer. The thickness of the second insulation layer is more than 5 nm. The gate electrode is formed of a p-type semiconductor containing p-type impurity.

Claims

1. A semiconductor memory cell allowing information to be written or erased electrically, said semiconductor memory cell comprising:

a first insulation layer;

an electric charge accumulating layer including an insulating material;

a second insulation layer including a silicon oxide film or a silicon oxynitride film, and being more than 5 nm in thickness; and

a control electrode formed on said second insulating layer and included a p-type semiconductor containing p-type impurity.

2. The semiconductor memory cell according to claim 1, wherein said first insulating layer including a silicon oxide film or a silicon oxynitride film, and the thickness of said second insulating layer is at least 1.8 nm larger than that of said first insulating layer.

3. The semiconductor memory cell according to claim 1, wherein said control electrode including silicon and the amount of said silicon is the largest of the plurality of elements contained in said control electrode.

4. The semiconductor memory cell according to claim 1, wherein a density of said p-type impurity of said control electrode is more than 2×

10¹⁹ (cm<sup>−

3</sup>) and less than 1×

10²⁰ (cm<sup>−

3</sup>).

5. A semiconductor memory cell allowing information to be written or erased electrically, said semiconductor memory cell comprising:

a gate insulation film having a multi-layer structure including three layers, said gate insulation film being included a first insulation layer, an electric charge accumulating layer and a second insulation layer, said electric charge accumulating layer being included a silicon nitride film or a silicon oxynitride film, said first insulation layer and second insulation layer being included a silicon oxide film or a silicon oxynitride film containing more oxygen composition than said electric charge accumulating layer, said second insulation layer being more than 5 nm in thickness; and

a control electrode formed on said gate insulation film and included a p-type semiconductor containing p-type impurity.

6. The semiconductor memory cell according to claim 5, wherein the thickness of said second insulation layer is at least 1.8 nm larger than that of said first insulation layer.

7. The semiconductor memory cell according to claim 5, wherein said control electrode contains a plurality of elements including silicon and the amount of said silicon is the largest of the plurality of elements contained in said control electrode.

8. The semiconductor memory cell according to claim 5, wherein a density of said p-type impurity of said control electrode is more than 2×

10¹⁹ (cm<sup>−

3</sup>) and less than 1×

10²⁰ (cm<sup>−

3</sup>).

9. A semiconductor memory device comprising:

a semiconductor memory cell constituted of an electric field effect transistor allowing information to be written or erased electrically, said semiconductor memory cell having;

a source region and a drain region each of a second conductive type formed in a semiconductor region of a first conductive type;

a gate insulation film formed on said semi-conductor region, said gate insulation film having a multi-layer structure including three layers, said gate insulation film being included a first insulation film, an electric charge accumulating layer and a second insulation layer, said electric charge accumulating layer being included a silicon oxide film or a silicon oxynitride film, said first insulation layer and second insulation layer being included a silicon oxide film or a silicon oxynitride film containing more oxygen composition than said electric charge accumulating layer, said second insulation layer being more than 5 nm in thickness; and

a control electrode formed on said gate insulation film and included a p-type semiconductor containing p-type impurity,

wherein said electric field effect transistor has an operation mode for, by applying a voltage which makes the voltage of the control electrode negative with respect to said source region or drain region to between said source region or said drain region and said control electrode so as to supply current between said source region or drain region and said electric charge accumulating layer, setting a threshold value of said electric field effect transistor more negative.

10. The semiconductor memory device according to claim 9, wherein when the voltage of said control electrode with respect to the potential of at least any one of said source region and said drain region is Vpp (V), assuming that the total film thickness of said gate insulation film, obtained by converting based on the silicon oxide film is teff (nm), the value of said voltage Vpp is set so as to satisfy −

1.0×

teff<

Vpp<

−

0.7×

teff−

1.

11. The semiconductor memory device according to claim 9, wherein when the voltage of said control electrode with respect to the potential of at least any one of said source region or said drain region is Vpp (V), assuming that the thickness of said first insulation layer is tox1 (nm), the thickness of the electric charge accumulating layer is tN (nm) and the thickness of the second insulation layer is tox2 (nm), the value of said voltage Vpp is set so as to satisfy −

1.0×

(tox1+tN/2+tox2)<

Vpp<

−

0.7×

(tox1+tN/2+tox2)−

1.

12. The semiconductor memory device according to claim 9, wherein the thickness of said second insulation layer is at least 1.8 nm larger than that of said first insulation layer.

13. A semiconductor memory device comprising:

a semiconductor memory cell constituted of a field effect transistor allowing information to be written or erased electrically, said semiconductor memory cell having;

a source region and a drain region each of a second conductive type formed in a semiconductor region of a first conductive type;

a gate insulation film formed on said semi-conductor region, said gate insulation film having a multi-layer structure including three layers, said gate insulation film being included a first insulation film, an electric charge accumulating layer and a second insulation layer, said electric charge accumulating layer being included a silicon oxide film or a silicon oxynitride film, said first insulation layer and second insulation layer being included a silicon oxide film or a silicon oxynitride film containing more oxygen composition than said electric charge accumulating layer, said second insulation layer being more than 5 nm in thickness; and

a control electrode formed on said gate insulation film and included a p-type semiconductor containing p-type impurity,

wherein said electric field effect transistor has such an operation mode for, by applying a voltage which makes the voltage of the control electrode negative with respect to said semiconductor region to between said semiconductor region and said control electrode so as to supply current between said semiconductor region and said electric charge accumulating layer, setting the threshold value of said electric field effect transistor more negative.

14. The semiconductor memory device according to claim 13, wherein when the voltage of said control electrode with respect to the potential of said semiconductor region is Vpp (V), assuming that the total film thickness of said gate insulation film, obtained by converting based on the silicon oxide film is teff (nm), the value of said voltage Vpp is set so as to satisfy −

1.0×

teff<

Vpp<

−

0.7×

teff−

1.

15. The semiconductor memory device according to claim 13, wherein when the voltage of said control electrode with respect to the potential of said semiconductor region is Vpp (V), assuming that the thickness of said first insulation layer is tox1 (nm), the thickness of the electric charge accumulating layer is tN (nm) and the thickness of the second insulation layer is tox2 (nm), the value of said voltage Vpp is set so as to satisfy −

1.0×

(tox1+tN/2+tox2)<

Vpp<

−

0.7×

(tox1+tN/2+tox2)−

1.

16. The semiconductor memory device according to claim 13, wherein when said operation mode is selected, direct tunnel current or Fowler-Nordheim tunnel current is supplied between said semiconductor region and said electric charge accumulating layer.

17. The semiconductor memory device according to claim 13, wherein when said operation mode is selected, direct tunnel current is supplied between said semiconductor region and said electric charge accumulating layer.

18. The semiconductor memory device according to claim 13, wherein the thickness of said second insulation layer is at least 1.8 nm larger than that of said first insulation layer.

19. A semiconductor memory device comprising:

at least one memory cell unit including a plurality of electric field effect transistors connected in series,

a pair of select transistors connected to an end and the other end of said at least one memory cell unit; and

a data transmission line connected to one of said pair of select transistors,

wherein each of said plurality of field effect transistors including;

a source region and a drain region each of a second conductive type formed in a semiconductor region of a first conductive type;

a gate insulation film formed on said semiconductor region, said gate insulation film having a multi-layer structure including three layers, said gate insulation film being included a first insulation film, an electric charge accumulating layer and a second insulation layer, said electric charge accumulating layer being included a silicon oxide film or a silicon oxynitride film, said first insulation layer and second insulation layer being included a silicon oxide film or a silicon oxynitride film containing more oxygen composition than said electric charge accumulating layer, said second insulation layer being more than 5 nm in thickness; and

a control electrode formed on said gate insulation film and included a p-type semiconductor containing p-type impurity.

20. The semiconductor memory device according to claim 19, wherein the thickness of said second insulation layer is at least 1.8 nm larger than that of said first insulation layer.

21. The semiconductor memory device according to claim 19, wherein a density of said p-type impurity of said control electrode is more than 2×

10¹⁹ (cm<sup>−

3</sup>) and less than 1×

10²⁰ (cm<sup>−

3</sup>).

22. The semiconductor memory device according to claim 19, wherein each of said pair of select transistors has a control electrode, said control electrode of select transistor composed of a p-type semiconductor containing p-type impurity.

23. The semiconductor memory device according to claim 19, wherein said at least one memory cell unit comprises a plurality of memory cell units,

said semiconductor memory device further comprising;

a plurality of data transmission lines;

a plurality of data select lines disposed so as to intersect said plurality of data transmission lines, and connected to said control electrode of said plurality of electric field effect transistors; and

a pair of control lines disposed in parallel to said plurality of data select lines, said pair of control lines supplying a control signal to said pair of select transistors,

wherein said plurality of memory cell units being disposed in parallel to each other in a direction intersecting said plurality of data transmission lines.

24. A semiconductor memory device comprising a semiconductor memory cell constituted of a field effect transistor allowing information to be written or erased electrically, said semiconductor memory cell having:

a source region and a drain region each of a second conductive type formed in a semiconductor region of a first conductive type;

a gate insulation film formed on said semiconductor region, said gate insulation film having a multi-layer structure including three layers, said gate insulation film being included a first insulation film, an electric charge accumulating layer and a second insulation layer, said electric charge accumulating layer being included a silicon oxide film or a silicon oxynitride film, said first insulation layer and second insulation layer being included a silicon oxide film or a silicon oxynitride film containing more oxygen composition than said electric charge accumulating layer, said second insulation layer being more than 5 nm in thickness; and

a control electrode formed on said gate insulation film and included a p-type semiconductor containing p-type impurity,

wherein said electric field effect transistor has such an operation mode for, by applying a voltage which makes the voltage of the control electrode negative with respect to said source region or drain region to between said source region or said drain region and said control electrode so as to supply current between said source region or drain region and said electric charge accumulating layer, setting the threshold value of said electric field effect transistor more negative, and

when the voltage of said control electrode with respect to the potential of said source region or drain region is Vpp (V), assuming that the total film thickness of said gate insulation film, obtained by converting based on the silicon oxide film is teff (nm), the value of said voltage Vpp is set so as to satisfy −

1.0×

teff<

Vpp<

−

0.7×

teff−

1.

25. The semiconductor memory device according to claim 24, wherein when the voltage of said control electrode with respect to the potential of said source region or drain region is Vpp (V), assuming that the thickness of said first insulation layer is tox1 (nm), the thickness of the electric charge accumulating layer is tN (nm) and the thickness of the second insulation layer is tox2 (nm), the value of said voltage Vpp is set so as to satisfy −

1.0×

(tox1+tN/2+tox2)<

Vpp<

−

0.7×

(tox1+tN/2+tox2)−

1.

26. The semiconductor memory device according to claim 24, wherein when said operation mode is selected, hot hole current is supplied between said source region or drain region and said electric charge accumulating layer.

27. The semiconductor memory device according to claim 24, wherein the thickness of said second insulation layer is at least 1.8 nm larger than that of said first insulation layer.

28. The semiconductor memory cell according to claim 24, wherein a density of said p-type impurity of said control electrode is 2×

10¹⁹ (cm<sup>−

3</sup>) or more and less than 1×

10²⁰ (cm<sup>−

3</sup>).

29. A semiconductor memory device comprising:

a first semiconductor region of a first conductivity type formed in a semiconductor substrate;

a memory cell transistor formed in said first semiconductor region allowing information to be written or erased electrically;

a second semiconductor region of a second conductivity type formed in said semiconductor substrate; and

a transistor formed in said second semiconductor region,

wherein said memory cell transistor having;

a first source region and a first drain region each of a second conductivity type formed in said first semiconductor region;

a gate insulation film formed on said first semiconductor region and having a multi-layer structure including three layers, said gate insulation film being included a first insulation layer, an electric charge accumulating layer and a second insulation layer, said electric charge accumulating layer being included a silicon nitride film or a silicon oxynitride film, said first insulation layer and second insulation layer being included a silicon oxynitride film containing a larger oxygen content than silicon oxide film or said electric charge accumulating layer, said second insulation layer being more than 5 nm in thickness, said first control electrode containing p-type impurity; and

a first control electrode formed on said gate insulation film,

wherein said transistor having;

a second source region and a second drain region each of said first conductivity type formed in said second semiconductor region; and

a second control electrode formed on said second semiconductor region through a third insulation layer and containing the p-type impurity.

30. The semiconductor memory device according to claim 29, wherein the thickness of said second insulation layer is at least 1.8 nm larger than that of said first insulation layer.

31. The semiconductor memory device according to claim 29, wherein a density of the p-type impurity in said first and second control electrodes is 2×

10¹⁹ (cm<sup>−

3</sup>) or more and less than 1×

10²⁰ (cm<sup>−

3</sup>), respectively.

32. The semiconductor memory device according to claim 29, wherein said third insulation layer is included a silicon oxide film which is less than 20 nm in thickness.

33. The semiconductor memory device according to claim 29, wherein said first control electrode and second control electrode have a multi-layer structure of metallic silicide and semiconductor, respectively.