Semiconductor device

• US 20030042965A1
• Filed: 08/05/2002
• Published: 03/06/2003
• Est. Priority Date: 08/31/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kanno, Yusuke, Yanagisawa, Kazumasa, Mizuno, Hiroyuki
• Granted Patent: US 6,700,429 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

Claims

1. A semiconductor device including a differential level converter circuit that receives a first signal and outputs a second signal of a larger amplitude than an amplitude of the first signal, the differential level converter circuit comprises a first MISFET pair for receiving the first signal;

a second MISFET pair for improving a withstand voltage of the first MISFET pair; and

a third MISFET pair having cross-coupled gates for latching the second signal from output,

wherein a film thickness of gate insulating films of the second MISFET pair is thicker than a film thickness of gate insulating films of the first MISFET pair;

wherein a film thickness of gate insulating films of the third MISFET pair is thicker than the film thickness of the gate insulating films of the first MISFET pair;

wherein an absolute value of a threshold voltage of the second MISFET pair is smaller than an absolute value of a threshold voltage of the third MISFET pair; and

wherein an absolute value of a threshold voltage of the first MISFET pair is smaller than the absolute value of the threshold voltage of the third MISFET pair.

2. The semiconductor device according to claim 1, wherein the gate insulating films of the second MISFET pair and the third MISFET pair are formed in one process and the insulating films of the first MISFET pair are formed in another process.

3. The semiconductor device according to claim 1, wherein the level converter circuit further comprises a first gate boosting circuit that boosts the first signal with the amplitude of the first signal to form a third signal with an amplitude bigger than the amplitude of the first signal so as to supply the third signal to one gate of the second MISFET pair;

and

a second gate boosting circuit that boosts a phase-inverted signal of the first signal with the amplitude of the first signal to form a fourth signal with an amplitude bigger than the amplitude of the first signal so as to supply the fourth signal to the other gate of the second MISFET pair.

4. The semiconductor device according to claim 1, wherein a source-drain path of one MISFET of each MISFET pair is connected in series and a source-drain path of the other MISFET of each MISFET pair is also connected in series, such that the second MISFET pair is arranged between the first MISFET pair and the third MISFET pair.

5. The semiconductor device according to claim 1, wherein the gate insulating films of the first MISFET pair are made of a material with a dielectric constant higher than the dielectric constant of silicon dioxide.

6. The semiconductor device according to claim 1, wherein the differential level converter circuit outputs a first differential output from one drain of the third MISFET pair and a second differential output from the other drain of the third MISFET pair, and

the semiconductor device further includes a level transition detector that defects and outputs a first-in-time edge transition of one of the first differential output and the second differential output.

7. The semiconductor device according to claim 6, wherein the level transition detector includes an RS flip-flop, an inverter, an OR gate, and a NAND gate,

the first differential output is input to a first input node of the RS flip-flop and the inverter,

the second differential output is input to a second input node of the RS flip-flop and a first input node of the OR gate,

an output of the RS flip-flop is input to a second input node of the OR gate, and

an output of the OR gate and an output of the inverter are input to the NAND gate.

8. The semiconductor device according to claim 6, wherein

the level transition detector includes an RS flip-flop, a NAND gate, and a D flip-flop,

the first differential output is input to a first input node of the RS flip-flop,

the second differential output is input to a second input node of the RS flip-flop,

a phase-inverted signal of the first differential input is input to a first input node of the NAND gate,

a phase-inverted signal of the second differential input is input to a second input node of the NAND gate,

an output of the NAND gate is input to the D flip-flop as a clock;

and

an output of the RS flip-flop is input to the D flip-flop as data.

9. The semiconductor device according to claim 1,

wherein the first signal has an amplitude being defined between a low level of a first potential and a high level of a second potential,

wherein the second signal has an amplitude being defined between a low level of a first potential and a high level of a third potential,

wherein the differential level converter circuit outputs the second signal including a first differential output from one drain of the third MISFET and a second differential output from the other drain of the third MISFET, and

wherein the semiconductor device further includes a second level converter circuit for receiving the first and second differential outputs and for outputting a third signal with an amplitude defined between a low level of a fourth potential being lower than the first potential and a high level of the third potential

10. The semiconductor device according to claim 1, wherein the first MISFET pair and the second MISFET pair are N-channel MISFETs, and the third MISFET pair are P-channel MISFETs.

11. A semiconductor device including a differential level converter circuit that receives a first signal and outputs a second signal with a larger amplitude than an amplitude of the first signal,

wherein the differential level converter circuit comprises a first MISFET pair for receiving the first signal;

a second MISFET pair for improving the withstand voltages of the first MISFET pair; and

a third MISFET pair having cross-coupled gates for latching the second signal from output, and

wherein the second MISFET pair and the third MISFET pair have higher withstand voltages than a withstand voltage of the first MISFET pair;

the second MISFET pair has a threshold voltage with an absolute value smaller than an absolute value of a threshold voltage of the third MISFET pair; and

the first MISFET pair has a threshold voltage with an absolute value smaller than an absolute value of a threshold voltage of the third MISFET pair.

12. A semiconductor device including a level converter circuit that receives a first signal with an amplitude of a first voltage and outputs a second signal with an amplitude of a second voltage which is larger than the first voltage;

wherein the level converter circuit comprises a first MISFET, a second MISFET, a third MISFET, and a fourth MISFET with source-drain paths therein connected in series having the second voltage applying therebetween; and

a fifth MISFET, a sixth MISFET, a seventh MISFET, and an eighth MISFET with source-drain paths therein connected in series having the second voltage applying therebetween; and

wherein

the first and third MISFETs receive the first signal at gates therein;

the fifth and seventh MISFETs receive a phase-inverted signal of the first signal at gates therein;

a gate of the fourth MISFET is coupled to a drain of the seventh MISFET;

a gate of the eighth MISFET is coupled to a drain of the third MISFET;

a drain of the third MISFET outputs a first differential output as the second signal;

a drain of the seventh MISFET outputs a second differential output which is a phase-inverted signal of the first differential output signal;

each of the first and fifth MISFETs is of a first conducting type and has a gate insulating film;

each of the third, fourth, seventh, and eighth MISFETs is of a second conducting type and has a gate insulating film thicker than the gate insulating film of each of the first and fifth MISFETs;

each of the second and sixth MISFETs has a gate insulating film thicker than the gate insulting film of each of the first and fifth MISFETs and has a threshold voltage lower than a threshold voltage of each of the third, fourth, seventh, and eighth MISFETs.

13. The semiconductor device according to claim 12, wherein each of the second and sixth MISFETs is of the first conducting type.

14. The semiconductor device according to claim 12, wherein

the gate insulating film of each of the first and fifth MISFETs is formed in one manufacturing process;

and

the gate insulating film of each of the second, third, fourth, sixth, seventh, and eighth MISFETs is formed in another manufacturing process.

15. The semiconductor device according to claim 12, wherein:

the level converter circuit further includes a ninth MISFET that receives the first signal at the gate therein and the second voltage at a source therein, and has a drain therein coupled with a drain of the first MISFET, and a tenth MISFET that receives the phase-inverted signal of the first signal at a gate therein and the second voltage at a source therein, and has a drain coupled with a drain of the fifth MISFET,

the second MISFET receives the first signal at a gate therein, and

the sixth MISFET receives the phase-inverted signal of the first signal at a gate therein.

16. The semiconductor device according to claim 12, wherein the level converter circuit further comprises a slave-latch circuit for fixing potential levels of drains of the third MISFET and the seventh MISFET.

17. The semiconductor device according to claim 12, further comprising a reset circuit provided at a stage prior to the level converter circuit,

wherein the reset circuit applies a NAND operation on a source signal of the first signal and a control signal to provide the first signal to the level converter circuit;

and

wherein the reset circuit includes an eleventh MISFET with a gate therein controlled by the control signal to fix the first differential output from the level converter circuit at the second voltage when the control signal indicates a reset state.

18. The semiconductor device according to claim 12 further comprising a level keeping circuit for keeping absolute values of voltages at the drain nodes of the first MISFET and the fifth MISFET smaller than an absolute value of the first voltage.

19. The semiconductor device according to claim 12 further comprising a level keeping circuit including:

an eleventh MISFET with a source-drain path connected between a drain of the first MISFET and the first voltage, and a gate therein being connected to the first voltage; and

a twelfth MISFET with a source-drain path connected between a drain of the fifth MISFET and the first voltage, and a gate therein being connected to the first voltage.

20. The semiconductor device according to claim 13, wherein the first conducting type is an N type, and the second conducting type is a P type.

21. The semiconductor device according to claim 12, further comprising:

a level transition detector that detects and outputs a first-in-time edge transition of one of the first differential output and the second differential output; and

a rest circuit for fixing output of the level transition detector,

wherein the level converter circuit further comprises a first power switch for supplying the second voltage to the level converter circuit.

22. The semiconductor device according to claim 21,

wherein when a rest signal is applied to the semiconductor device, the reset circuit sets the output of the level transition detector to a predetermined voltage level, and the first power switch stops supplying the second voltage to the level converter circuit.