Multi-master bus architecture for system -on-chip designs
First Claim
1. A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves, wherein each bus master and each bus slave has at least a port in and a port out, the system comprising:
- a plurality of multiplexers in communication with each data in port of each bus master and each bus slave;
a plurality of isolated data paths connecting the port out of each bus master to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design; and
distributed arbitration to allow each bus slave to be selected independently of other bus slaves.
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Abstract
A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves. The system includes a plurality of multiplexers in communication with each data in port of each bus master and each bus slave. The system also includes a plurality of isolated data paths connecting the port out of each bus master to each multiplexer in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design. In addition a distributed arbitration is included to allow each bus slave to be selected independently of the other bus slaves.
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Citations
19 Claims
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1. A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves, wherein each bus master and each bus slave has at least a port in and a port out, the system comprising:
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a plurality of multiplexers in communication with each data in port of each bus master and each bus slave;
a plurality of isolated data paths connecting the port out of each bus master to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design; and
distributed arbitration to allow each bus slave to be selected independently of other bus slaves. - View Dependent Claims (3, 4, 5, 6)
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2. The bus architecture system of claim 2, wherein the distributed arbitration includes an arbiter in communication with each multiplexer that is in communication with the data in port of each bus slave.
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7. A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves, wherein each bus master and each bus slave has at least a port in and a port out, the system comprising:
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a plurality of multiplexers in communication with each data in port of each bus master and each bus slave;
a plurality of isolated data paths connecting the port out of each bus master to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design; and
distributed address decoding to allow each master to have a tailored address map. - View Dependent Claims (8, 9, 10)
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11. A bus architecture system on an integrated circuit comprising:
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a plurality of pairs of data ports, each pair of data ports defines a data in port and a data out port, and each pairs of data ports correspond to a either a bus master or a bus slave;
a plurality of multiplexers in communication with each data in port;
a plurality of isolated data paths connecting the data out port corresponding to a bus master to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus slave, and a plurality of isolated data paths connecting the data out port corresponding to a bus slave to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus master, thereby providing concurrency on the system on chip design; and
an arbiter in communication with each multiplexer that is in communication with a data in port corresponding to a bus slave. - View Dependent Claims (12, 13, 14, 15, 18, 19)
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16. A bus architecture system on an integrated circuit comprising:
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a plurality of pairs of data ports, each pair of data ports defines a data in port and a data out port, and each pairs of data ports correspond to a either a bus master or a bus slave;
a plurality of multiplexers in communication with each data in port;
a plurality of isolated data paths connecting the data out port corresponding to a bus master to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus slave, and a plurality of isolated data paths connecting the data out port corresponding to a bus slave to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus master, thereby providing concurrency on the system on chip design; and
an address decoder in communication with each multiplexer that is in communication with a data in port corresponding to a bus master. - View Dependent Claims (17)
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Specification