Semiconductor structure and method for determining critical dimensions and overlay error

• US 20030044702A1
• Filed: 04/29/2002
• Published: 03/06/2003
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schulz, Bernd
• Granted Patent: US 6,767,680 B2
• Time in Patent Office: Days
• US Class Current: 430/30
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

Abstract

A semiconductor structure and a method of determining an overlay error produced during formation of a semiconductor structure is disclosed. The semiconductor structure comprises a first periodic pattern and a second periodic pattern, which overlap with each other, wherein a relative position between the overlapping first and second periodic patterns contains information on the magnitude and the sign of an overlay error in a predefined direction that has been caused during the formation of the first and second periodic patterns. The overlay error is determined by directing a light beam of known optical properties onto the first and second periodic patterns and by analyzing the diffracted beam by comparison with reference data. By providing two differently oriented diffracting areas, each comprising first and second periodic patterns, the overlay error in two dimensions can be determined.

Claims

1. A semiconductor structure for metrology of critical dimensions and overlay accuracy, the semiconductor structure comprising:

a substrate with one or more material layers formed thereon;

a first periodic pattern having a first periodicity along a predefined direction;

a second periodic pattern having a second periodicity along said predefined direction;

wherein the first and second periodic patterns are positioned to overlap with each other such that a relative displacement of the first periodic pattern and the second periodic pattern is indicative of an overlay error of the first and second periodic patterns with respect to the predefined direction.

2. The semiconductor structure of claim 1, wherein the first periodic pattern comprises first and second regions defining the first periodicity, and the second periodic pattern comprises first and second regions defining the second periodicity, whereby each of the first and second regions of the first periodic pattern overlaps with a first and a second region of the second periodic pattern.

3. The semiconductor structure of claim 1, wherein the first and second periodicities are substantially equal.

4. The semiconductor structure of claim 1, wherein the first and second periodicities are different.

5. The semiconductor structure of claim 1, wherein the first periodic pattern is formed as a first grating.

6. The semiconductor structure of claim 5, wherein the first grating is comprised of a plurality of first regions comprised of a plurality of lines of a first material, and a plurality of second regions comprised of lines of a second material.

7. The semiconductor structure of claim 5, wherein the first grating is formed by lines and spaces.

8. The semiconductor structure of claim 5, wherein a width of the first and second regions forming the first grating is substantially equal.

9. The semiconductor structure of claim 5, wherein the first and the second regions of the first grating differ from each other in at least one of an index of refraction, a surface texture, and birefringence.

10. The semiconductor structure of claim 5, wherein the second periodic pattern is a second grating.

11. The semiconductor structure of claim 10, wherein the second grating is comprised of a plurality of lines and spaces as first and second regions, respectively.

12. The semiconductor structure of claim 10, wherein the second grating is comprised of a plurality of lines of a first material and lines of a second material.

13. The semiconductor structure of claim 1, further comprising a scribe lane, wherein the first and second periodic patterns are located in the scribe lane.

14. The semiconductor structure of claim 1, further comprising:

a third periodic pattern having a third periodicity along a second predefined direction; and

a fourth periodic pattern having a fourth periodicity along the second predefined direction, wherein the third and fourth periodic patterns are positioned to overlap with each other and wherein a relative displacement of the third periodic pattern and the fourth periodic pattern is indicative for an overlay error of the third and fourth periodic patterns along the second predefined direction.

15. The semiconductor structure of claim 14, wherein the predefined direction and the second predefined direction are substantially perpendicular to each other.

16. A semiconductor structure for metrology of critical dimensions and overlay accuracy, the semiconductor structure comprising:

a substrate with at least one material layer formed thereon;

a plurality of first regions formed in the at least one material layer;

a plurality of second regions formed in the at least one material layer;

a plurality of third regions, each third region located between a first region and a second region;

wherein the first, second and third regions define a grating having a periodicity along a predefined direction, whereby a relative position of each third region with respect to the first and second regions is indicative for an overlay error caused by forming the third regions.

17. A method of determining an overlay error caused during formation of a semiconductor structure, the method comprising:

(a) providing the semiconductor structure comprising;

a first periodic pattern; and

a second periodic pattern, said first and second periodic patterns positioned to overlap one another, wherein a relative position between the first periodic pattern and the second periodic pattern is indicative for an overlay error caused during formation of the first and second periodic patterns;

(b) directing a light beam onto the first and second periodic patterns;

(c) detecting a light beam diffracted by the first and second periodic patterns to generate a measurement spectrum; and

(d) comparing the measurement spectrum with reference data, wherein the reference data represents information for a predefined overlay error of the first and second periodic patterns with respect to a predefined direction.

18. The method of claim 17, wherein said light beam is a multi-wavelength light beam.

19. The method of claim 17, wherein said light beam is a substantially linearly polarized light beam.

20. The method of claim 17, wherein a plane of incidence of the light beam impinging on the first and second periodic patterns is selected to substantially coincide with the predefined direction.

21. The method of claim 17, wherein the semiconductor structure further comprises a third periodic pattern and a fourth periodic pattern, said third and fourth periodic patterns positioned to overlap one another, wherein a relative position of the third and fourth periodic patterns is indicative for an overlay error with respect to a second predefined direction.

22. The method of claim 21, wherein the predefined direction and the second predefined direction are substantially orthogonal to each other.

23. The method of claim 22, further comprising:

(e) directing a second light beam onto the third and fourth periodic patterns;

(f) detecting a light beam diffracted by the third and fourth periodic patterns to generate a second measurement spectrum; and

(g) comparing the second measurement spectrum with reference data, wherein the reference data represents information for a predefined overlay error of the third and fourth periodic patterns with respect to the second predefined direction.

24. The method of claim 23, wherein the steps (b) to (d) and the steps (e) to (g) are performed substantially simultaneously.

25. The method of claim 23, wherein the steps (b) to (d) and the steps (e) to (g) are performed in a sequential manner.

26. The method of claim 25, wherein step (e) is performed by rotating the substrate.

27. The method of claim 25, wherein step (e) is performed by deflecting said light beam to create the second light beam.