Method to prevent electrical shorts between adjacent metal lines

• US 20030045108A1
• Filed: 05/21/2002
• Published: 03/06/2003
• Est. Priority Date: 09/04/2001
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Hsu, Ping, Tsai, Tzu-Ching
• Granted Patent: US 6,831,016 B2
• Time in Patent Office: Days
• US Class Current: 438/692
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

A method to prevent electrical shorts between adjacent metal lines on a semiconductor substrate having an insulating layer with a pair of damascene structures connecting to the semiconductor substrate and a scratch on the upper surface of the insulating layer, between the damascene structures, is provided. A diffusion barrier layer is deposited on the damascene structures and the scratch. Then, a metal layer is formed to fill the damascene structures. Next, the metal is chemical-mechanically polished to form a metal line. Finally, the diffusion barrier layer disposed on the surface of the scratch is removed by etching process.

Claims

1. A method to prevent electrical shorts between adjacent metal lines on a semiconductor substrate having an insulating layer with a pair of damascene structures connecting to the semiconductor substrate and a scratch on the upper surface of the insulating layer between the damascene structures, comprising the steps of:

(a) forming a diffusion barrier layer on the pair of damascene structures and the scratch;

(b) forming a metal layer to fill the pair of damascene structures;

(c) chemical mechanical polishing the metal layer to form a metal line; and

(d) removing the diffusion barrier layer disposed on the surface of the scratch by etching.

2. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the insulating layer is silicon oxide deposited by tetra-ethyl-ortho-silicate (TEOS).

3. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the diffusion barrier layer is a titanium nitride layer.

4. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the diffusion barrier layer is a titanium nitride layer.

5. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 3 or 4, wherein the metal layer is a tungsten layer.

6. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the etching process in step (e) is reactive ion etching (RIE).

7. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the diffusion barrier layer has an selectivity of about 6:

1 to about 7;

1 with respect to the metal line.

8. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the the etching process in step (e) uses an etching gas containing chlorine.