Signal processing circuit outputting a signal representing the number of times an input signal rises in a predetermined period as a signal corresponding to a quality of the input signal

• US 20030046037A1
• Filed: 08/23/2002
• Published: 03/06/2003
• Est. Priority Date: 09/06/2001
• Status: Active Grant

• Current Assignee: FAS Controls Inc.
• Original Assignee: TEAC Corporation
• Inventors: Mashimo, Akira
• Granted Patent: US 6,954,709 B2
• Time in Patent Office: Days
• US Class Current: 702/189
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels

Abstract

A signal processing circuit outputs a signal corresponding to a quality of a digitized input signal. An edge counter of the signal processing circuit counts the number of times the input signal rises and/or falls in a predetermined period. An output unit of the signal processing circuit outputs a signal representing the number of times counted by the edge counter. This signal is output as the signal corresponding to the quality of the input signal.

Claims

1. A signal processing circuit outputting a signal corresponding to a quality of a digitized input signal, the circuit comprising:

an edge counter counting a number of times said input signal rises and/or falls in a predetermined period; and

an output unit outputting a signal corresponding to said number of times as the signal corresponding to the quality of said input signal.

2. The signal processing circuit as claimed in claim 1, wherein said predetermined period is predetermined by cycles of said input signal.

3. The signal processing circuit as claimed in claim 1, further comprising a noise-removed signal generation unit generating a noise-removed signal from said input signal, the noise-removed signal excluding a noise component,

wherein said predetermined period is between two times at which a polarity of said noise-removed signal is inverted.

4. The signal processing circuit as claimed in claim 3, wherein said noise-removed signal generation unit comprises a cumulative time counting unit counting a cumulative time in which said input signal is at one of a high-level state and a low-level state;

and

a retention unit performing one of a setting and a resetting of a high-level state according to said cumulative time, and clearing said cumulative time according to said state,

wherein said edge counter counts the number of times said input signal rises and/or falls in a period after said retention unit performs one of the setting and the resetting of the high-level state until next time said retention unit performs one of the setting and the resetting of the high-level state.

5. The signal processing circuit as claimed in claim 4, wherein said cumulative time counting unit comprises a gate unit outputting a predetermined clock according to said input signal;

and

a counting unit counting said predetermined clock,

wherein said retention unit performs one of the setting and the resetting of the high-level state according to a count value of said counting unit, and clears said count value of said counting unit according to said state.

6. The signal processing circuit as claimed in claim 5, wherein said gate unit comprises a first gate unit outputting the predetermined clock during a period in which said input signal is at the high-level state;

and

a second gate unit outputting the predetermined clock during a period in which said input signal is at the low-level state, and

said counting unit comprises a first counting unit counting said predetermined clock output from said first gate unit; and

a second counting unit counting said predetermined clock output from said second gate unit,

wherein said retention unit-performs the setting of the high-level state and clears a count value of said second counting unit when a count value of said first counting unit reaches a first count value, and performs the resetting of the high-level state and clears the count value of said first counting unit when the count value of said second counting unit reaches a second count value

7. The signal processing circuit as claimed in claim 5, further comprising a latch circuit latching a count value of said edge counter when the count value of said counting unit reaches a predetermined value;

and

a delay circuit delaying an output of said counting unit by a predetermined time,

wherein said edge counter is cleared according to an output of said delay circuit.

8. The signal processing circuit as claimed in claim 1, further comprising a quality judgment unit judging the quality of said input signal according to the signal output by said output unit.

9. The signal processing circuit as claimed in claim 3, further comprising a quality judgment unit judging the quality of said input signal according to the signal output by said output unit.

10. The signal processing circuit as claimed in claim 8, wherein said quality judgment unit judges that the quality of said input signal is aggravated when said number of times represented by said signal output by said output unit exceeds a predetermined number of times.

11. The signal processing circuit as claimed in claim 9, wherein said quality judgment unit judges that the quality of said input signal is aggravated when said number of times represented by said signal output by said output unit exceeds a predetermined number of times.

12. The signal processing circuit as claimed in claim 8, wherein said quality judgment unit judges that the quality of said input signal is more aggravated as said number of times represented by said signal output by said output unit becomes larger.

13. The signal processing circuit as claimed in claim 9, wherein said quality judgment unit judges that the quality of said input signal is more aggravated as said number of times represented by said signal output by said output unit becomes larger.

14. The signal processing circuit as claimed in claim 1, further comprising a warning unit performing a predetermined warning to the effect that an abnormality occurs in said input signal when said number of times represented by said signal output by said output unit exceeds a predetermined number of times.

15. The signal processing circuit as claimed in claim 3, further comprising a warning unit performing a predetermined warning to the effect that an abnormality occurs in said input signal when said number of times represented by said signal output by said output unit exceeds a predetermined number of times.