System-on-a-chip with soft cache and systems and methods using the same

• US 20030046510A1
• Filed: 03/30/2001
• Published: 03/06/2003
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: North, Gregory Allen
• Granted Patent: US 6,622,208 B2
• Time in Patent Office: Days
• US Class Current: 711/203
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0886 Variable-length word access
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in virtual memory. A cache line size for the cache line is programmable. When the tag bits of the virtual address match the tag field of one of the soft cache entries, the index from that entry is selected for generating a physical address. The physical address is generated using the selected index as an offset to a corresponding soft cache space in memory.

Claims

1. A soft cache system performing the operations of:

comparing tag bits of a virtual address with tag bits programmed in a plurality of register entries, each entry associated with an index to a cache line of programmable cache line size in virtual cache space, the virtual cache space location programmed by a block address portion of the virtual address;

when the tag bits of the virtual address match the tag bits of one of the programmable register entries, selecting the index corresponding to said entry for generating a physical address; and

generating the physical address using the selected index as an offset to the cache line and the block address from the virtual memory as an address to the virtual cache space.

2. The soft cache system of claim 1 further performing the operations when the tag bits of the virtual address do not match the tag field of one of the register entries of:

selecting a cache line in the virtual cache space for encaching data associated with the virtual address;

retrieving the data from a second area of memory using the virtual address;

encaching the data in the selected cache line in the virtual cache space; and

updating the tag bits in the register associated with the selected cache line.

3. The soft cache system of claim 1 wherein the cache line size is programmable to be M number of locations and the virtual address includes log2M number of bits indexing the M number of cache line locations.

4. The soft cache system of claim 3 wherein the M number of locations comprise byte locations.

5. The soft cache system of claim 4 wherein the cache line size is selected from the group consisting of 128, 256, 512, and 1024 bytes.

6. The soft cache system of claim 1 wherein the cache system comprises an X-way set associative system having X number of register entries storing log2X number of tag bits.

7. The soft cache system of claim 6 wherein the cache system comprises a 16-way set associative system and the plurality of register entries each store 4 bits.

8. A method of data caching comprising the steps of:

setting up an M-way set associative cache comprising a register having M number of corresponding entries each storing a tag value and indexed to a cache line in a selected cache area in memory;

setting a cache line size for the cache lines, the cache tag value selected as a function of the selected cache line size;

generating a virtual address including a tag field, a cache line address field addressing locations within the cache line size and a block address field addressing the cache area in memory;

comparing the tag field of the virtual address with the tag values in the cache; and

when the tag field of the virtual address matches a tag value in the cache, generating a physical address to the corresponding cache line with the index associated with the register entry containing the matching tag value and the cache line and block address fields from the virtual address.

9. The method of claim 8 and further comprising the step of updating a history register with the index associated with the matching tag value.

10. The method of claim 9 and further comprising the steps of:

when the tag field of the virtual address does not match a tag value in the register, accessing a corresponding area in memory with the virtual address;

selecting a replacement cache line from the cache area in memory from information stored in the history register;

transferring data from the corresponding area in memory accessed with the virtual address to the replacement cache line in the cache area of memory; and

updating the register entry associated with the index to the replacement cache line with the tag from the virtual address.

11. The method of claim 9 wherein said step of updating the history register comprises the step of shifting an index into a shift register.

12. The method of claim 9 wherein said step of updating the history register comprises the step of storing a plurality of non-identical indices.

13. The method of claim 9 wherein said step of setting up a cache comprises the step of setting up a hardware register having a plurality of entries for storing a tag value and indexed to a cache line.

14. The method of claim 9 further comprising the steps of:

determining if a block address field of the virtual address corresponds to the cache area in memory; and

addressing the memory with the virtual address if the block address of the virtual address does not correspond to the cache area in memory.

15. The method of claim 9 wherein the cache area in memory comprises an area in random access memory.

16. The method of claim 9 wherein the cache area in memory comprises an area in FLASH memory.

17. A system comprising:

a central processing unit;

a memory including a soft cache space, and

a soft cache system for accessing data in the soft cache space in response to addresses from the central processing unit including;

a register having a plurality of entries each for storing a cache tag and indexed to a cache line in the soft cache space, the cache line having a programmable cache line size;

a plurality of comparators for comparing a tag field of an address from the central processing unit with cache tags stored in each of the entries of the register; and

circuitry for a generating an address to the soft cache space when the tag field matches a tag value in the register using the index associated with the entry storing the matching cache tag and selected bits from the address from the central processing unit addressing the soft cache space.

18. The system of claim 17 wherein said central processing unit comprises a portion of a system on a chip.

19. The system of claim 18 wherein said memory forms part of said system on a chip.

20. The system of claim 18 wherein said memory is external to said system on a chip.

21. The system of claim 17 wherein said central processing unit and said memory form part of a portable audio system.