Error method, system and medium

• US 20030046628A1
• Filed: 09/06/2001
• Published: 03/06/2003
• Est. Priority Date: 09/06/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rankin, Linda J., OʼShea, David J.
• Granted Patent: US 7,346,825 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0775 Content or structure details of the error report, e.g. specific table structure, specific error fields
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C

Abstract

Error methods, systems, and medium may comprise processing error conditions associated with transactions in a manner that may enable error source identification.

Claims

1. A system comprising

a first node of components comprising a processor, a memory controller, memory, and a node switch, the memory controller and the node switch each comprising a storage element to record an error condition indicative of whether at least one component provided an indication of detecting an error in response to processing a transaction;

and

a second node of components comprising a processor, a memory controller, memory, and a node switch coupled to the first node, the memory controller and the node switch each comprising a storage element to record an error condition indicative of whether at least one component provided an indication of detecting an error in response to processing a transaction.

2. The system of claim 1, wherein

the memory controllers and the node switches record the error condition in response to detecting an error with a transaction.

3. The system of claim 1, wherein

the memory controllers and the nodes switches record the error condition and an error type in their respective storage elements in response to detecting an error with a transaction.

4. A system comprising

a first component to provide an error condition indicative of whether the first component detected an error associated with a transaction;

and

a second component to record the error condition if the second component in response to processing the transaction detects an error.

5. The system of claim 4, wherein

the transaction provides error coverage information, and

the first component detects an error associated with the transaction based upon the error coverage information.

6. The system of claim 4, wherein

the transaction provides error coverage information, and

the first component corrects at least a subset of errors based upon the error coverage information.

7. The system of claim 4, wherein

the first component in response to detecting an error associated with the transaction poisons the transaction to ensure that the second component detects an error in response to processing the transaction.

8. The system of claim 4, further comprising a third component, wherein

the second component provides the third component with an updated error condition that is indicative of whether the second component detected an error in response to processing the transaction.

9. The system of claim 4, wherein

the first component comprises a first error condition interface, and

the second component comprises a second error condition interface coupled to the first error condition interface to receive the error condition.

10. A method comprising

receiving a plurality of error conditions, each associated with a component of a plurality of components and indicative of whether at least one other component detected an error in response to processing a transaction.

11. The method of claim 10, further comprising

receiving the plurality of error conditions in response to an error with the transaction.

12. The method of claim 10, further comprising

providing, based upon the plurality of error conditions, an indication as to which component of the plurality of components first detected an error with the transaction.

13. A method comprising

detecting an error associated with a transaction at a component of a plurality of components;

and

updating information associated with the component to record an error condition that is indicative of whether another component of the plurality of components detected an error with the transaction.

14. The method of claim 13, further comprising

providing another component of the plurality of components with an updated error condition that is indicative of the error being detected.

15. The method of claim 13, further comprising

asserting an error signal to provide another component of the plurality of components with an updated error condition that is indicative of the error being detected.

17. The method of claim 13, wherein

updating comprises recording in a register of the component the error condition and an error type for the error detected.

18. The method of claim 13, further comprising

receiving the error condition in band with the transaction;

and

providing an updated error condition and an error type in band with the transaction to another component of the plurality of components.

16. The method of clam 13, further comprising

receiving the error condition in band with the transaction;

and

providing an updated error condition in band with the transaction to another component of the plurality of components.

19. A method comprising

determining whether an error was detected in association with a transaction based upon a received error condition;

and

recording the received error condition in response to determining that an error was detected.

20. The method of claim 19, further comprising

providing an updated error condition in response to detecting an error with the transaction.

21. The method of claim 19, wherein

recording comprises storing information that is indicative of the error condition and an error type.

22. The method of claim 19, further comprising

correcting an error associated with the transaction based upon error coverage information of the transaction.

23. The method of claim 19, further comprising

determining that an error is uncorrectable based upon error coverage information of the transaction;

and

poisoning the transaction to ensure future detection of the error.

24. A component comprising

an error detection circuit to detect an error with a transaction;

and

a storage element to record an error condition provided by at least one other component if the error detection circuit detects an error with the transaction.

25. The component of claim 24, further comprising

an error correction circuit to correct at least a subset of errors detected by the error detection circuit.

26. The component of claim 24, further comprising

an error condition interface to receive the error condition provided by at least one other component, and to provide at least one other component with an updated error condition.

27. The component of claim 24, wherein

the storage element comprises a register to store the error condition and an error type associated with the detected error.

28. A machine readable medium comprising a plurality of instructions, that in response to being executed, result in at least one processor

receiving a plurality of error conditions associated with a transaction, each error condition associated with a component of a plurality of components and indicative of whether at least one other component detected an error in response to processing the transaction.

29. The machine readable medium of claim 28, wherein the plurality of instructions further result in the processor

receiving the plurality of error conditions in response to an error with the transaction being detected.

30. The machine readable medium of claim 28, wherein the plurality of instructions further result in the processor

determining, based upon the plurality of error conditions, which component of the plurality of components first detected an error with the transaction.