Edge termination in a trench-gate MOSFET

• US 20030047777A1
• Filed: 09/10/2002
• Published: 03/13/2003
• Est. Priority Date: 09/13/2001
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Inʼt Zandt, Michael A.A., Hijzen, Erwin A., Hueting, Raymond J.E.
• Granted Patent: US 6,833,583 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

To avoid premature breakdown at the edge of the active area of RESURF trench-gate MOS device, an edge field plate (24) can be placed with a connection to the gate and a second spaced field plate (24) in the same trench (12). The gate trench network (12) could be either formed by hexagon unit cells or by square unit cells. Since the RESURF condition requires a small cell pitch, self-aligned processing could be used.

Claims

1. A cellular trench-gate field-effect transistor comprises a semiconductor body having an array of transistor cells, the cells being bounded by a pattern of perimeter trenches lined with dielectric material around the perimeter of the array, the perimeter trench having an inner wall closer to an active area of the transistor and an outer wall closer to the edge of the transistor, characterised in that each of said inner and outer walls has a field plate located on the dielectric material and the field plate on the inner wall of the perimeter trench is connected to a source or trench-gate of the transistor.

2. A transistor as claimed in claim 1, in which the perimeter trench includes dielectric material between the field plates on the inner and outer walls.

3. A transistor as claimed in claim 1, in which each of said perimeter trenches has a field plate on said inner wall.

4. A transistor as claimed in claim 1, in which the field plates are formed of polysilicon.

5. A transistor as claimed in claim 1, in which the transistor cells and/or perimeter trenches are hexagon cells or square cells.

6. A transistor as claimed in claim 1, in which the inner wall field plate is connected to the trench-gate.

7. A transistor as claimed in claim 1, in which the active area extends beneath a gate bondpad of the transistor.

8. A method of manufacturing a trench-gate field-effect transistor comprises:

forming an array of transistor cells on a semiconductor body;

forming a pattern of perimeter trenches around the perimeter of the array of transistor cells

lining the perimeter trenches with dielectric material;

characterised by

forming an inner field plate on an inner wall of the perimeter trench closer to the array and forming an outer field plate on an outer wall of the perimeter trench closer to an edge of the transistor; and

connecting the inner field plate to a source or trench-gate of the transistor.

9. A method as claimed in claim 8, in which steps d) and e) are performed in a self-aligned manner.

10. A method as claimed in claim 8, in which step d) is performed by depositing a conductive layer in the perimeter trenches.

11. A method as claimed in claim 10, which is followed by etching said conductive layer anisotropically to remove the conductive layer from the bottom of the perimeter trench.

12. A method as claimed in claim 8, in which material for the trench-gate and a trench connection layer is deposited in the perimeter trenches and over an upper face of the pattern of perimeter trenches.

13. A method as claimed in claim 12, which includes subsequently etching away said material from the perimeter trenches to be replaced with a conductive layer that provides the inner and outer field plates.