Methods and apparatuses for multiple sampling and multiple pulse generation

• US 20030048212A1
• Filed: 08/13/2002
• Published: 03/13/2003
• Est. Priority Date: 06/06/2001
• Status: Active Grant

• Current Assignee: Furaxa, Inc.
• Original Assignee: Furaxa, Inc.
• Inventors: Chacko, Steven J., Libove, Joel M.
• Granted Patent: US 6,642,878 B2
• Time in Patent Office: Days
• US Class Current: 341/144
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A method and apparatus for generating multiple ultra-fast (picosecond-range) electrical sampling apertures and pulses in response to a slewed control signal is disclosed. In one embodiment a series or sequence of sampling apertures are formed for sampling an input signal without the use of delay lines. In another embodiment, the input to be sampled is incrementally delayed to generate signals along a delay line. The delayed signals are simultaneously sampled in a sampling window to obtain a group of samples of an input signal at the same time. In another embodiment, a series or sequence of ultra-fast pulses are formed in an output signal without using delay lines. Parallel and serial sampler/pulser circuitry are disclosed.

Claims

1. A serial multiple sampler circuit comprising:

a differential transistor pair having control terminals coupled to input terminals to receive a differential data input signal, the differential transistor pair jointly coupled to a current source at a first end;

a first sampler circuitry coupled between a second end of the differential transistor pair and a first output, the first sampler circuitry to receive a sample control signal, a third voltage level, and a second voltage level, the first sampler circuitry including level activated switching elements responsive to the sample control signal and the third voltage level to couple a first sample of the differential data input signal to the first output; and

a second sampler circuitry coupled between the second end of the differential transistor pair and a second output, the second sampler circuitry to receive the sample control signal, a second voltage level, and a first voltage level, the second sampler circuitry including level activated switching elements responsive to the sample control signal, the second voltage level, and the first voltage level to couple a second sample of the differential data input signal to the second output.

2. The serial multiple sampler circuit of claim 1 wherein,

the first sampler circuitry to sample the differential data input signal when a voltage of the sample control signal is between the third voltage level and the second voltage level.

3. The serial multiple sampler circuit of claim 1 wherein,

the second sampler circuitry to sample the differential data input signal when a voltage of the sample control signal is between the second voltage level and the first voltage level.

4. The serial multiple sampler circuit of claim 1 further comprising:

a third sampler circuitry coupled to the second sampler circuitry at one end and a third output at an opposite end,

a first level shifter to receive the sample control signal and generate a first level shifted sample control signal, and

wherein

the third sampler circuitry to receive the second voltage level and the first level shifted sample control signal, and

the third sampler circuitry including level activated switching elements responsive to the first level shifted sample control signal and the second voltage level to couple a third sample of the differential data input signal to the third output.

5. The serial multiple sampler circuit of claim 4 further comprising

a fourth sampler circuitry coupled to the third sampler circuitry at one end and a fourth output at an opposite end,

a second level shifter to receive the first level shifted sample control signal and generate a second level shifted sample control signal, and

wherein

the fourth sampler circuitry to receive the third voltage level and the second level shifted sample control signal, and

the fourth sampler circuitry including level activated switching elements responsive to the second level shifted sample control signal and the third voltage level to couple a fourth sample of the differential data input signal to the fourth output.

6. The serial multiple sampler circuit as in any of claims 1-5 wherein

sample times at which each of the multiple samples is acquired are dynamically altered by dynamically modulating the first, second and third voltage levels.

7. The serial multiple sampler circuit of claim 1 wherein,

the level switching elements are differentially paired transistors.

8. A serial multiple pulser circuit comprising:

a first differential input stage having a first control terminal coupled to a first single-ended input and a second control terminal coupled to a second single-ended input, the first differential stage coupled to a first current source at one end;

a second differential input stage having a first control terminal coupled to the first single-ended input and a second control terminal coupled to a low level power supply, the second differential stage coupled to a second current source at one end;

a first differentially-paired-transistors (DPT) having control terminals coupled to a second voltage level, drain terminals coupled to a high level power supply, and source terminals coupled to the first differential input stage;

a second DPT having control terminals coupled to a control signal, drain terminals coupled to the high level power supply, and source terminals coupled to a third DPT;

the third DPT having control terminals coupled to the control signal, drain terminals coupled to the source terminals of the second DPT, and source terminals coupled to the first differential input stage;

a fourth DPT having control terminals coupled to a third voltage level, drain terminals coupled to output terminals of an output, and source terminals coupled to the drain terminals of the third DPT, the source terminals of the second DPT, and drain terminals of a fifth DPT;

the fifth DPT having control terminals coupled to the control signal, drain terminals coupled to the source terminals of the fourth DPT, and source terminals coupled to the second differential input stage; and

a sixth DPT having control terminals coupled to a first voltage level, drain terminals coupled to a high level power supply, and source terminals coupled to the second differential input stage.

9. The serial multiple pulser circuit of claim 8 wherein,

the control signal to activate the serial multiple pulser circuit to generate at a common set of output terminals a first pulse responsive thereto when a voltage level of the control signal is between the third voltage level and the second voltage level, and

the control signal to activate the serial multiple pulser circuit to generate a second pulse on said common set of output terminals responsive thereto when a voltage level of the control signal is between the second voltage level and the first voltage level.

10. The serial multiple pulser circuit of claim 8 further comprising:

a first resistor and a second resistor each having one end coupled to the high level power supply and an opposite end coupled to the output terminals of the output.

11. The serial multiple pulser circuit of claim 8 wherein,

pulse widths of the pulses generated by the serial multiple pulser circuit are responsive to the first, second, and third voltage levels.

12. The serial multiple pulser circuit of claim 8 wherein

starting times of the pulses generated by the serial multiple pulser circuit are responsive to the first, second and third voltage levels.

13. The serial multiple pulser circuit of claim 11 wherein,

ending times of the pulses generated by the serial multiple pulser circuit are responsive to the first, second and third voltage levels.

14. The serial multiple pulser circuit of claim 13 wherein,

the pulses generated by the serial multiple pulser circuit are time shifted by altering the first, second and third voltage levels.

15. The serial multiple pulser circuit of claim 8 wherein,

starting times of the pulses are dynamically altered by dynamically modulating the first and second voltage levels.

16. The serial multiple pulser circuit of claim 8 wherein,

amplitudes of the pulses generated by the serial multiple pulser circuit are responsive to voltage levels of the first input and the second input.

17. A multiple sampler circuit comprising:

a differential transistor pair having control terminals coupled to input terminals to receive a differential data input signal, source terminals jointly coupled to a current source at a first end, and drain terminals separately coupled to a serial string of differential delay lines at a second end opposite the first end;

the serial string of differential delay lines including a plurality of differential delay lines coupled in series together, the serial string of differential delay lines having a first end and a second end, the first end coupled to the differential transistor pair, the serial string of differential delay lines forming a plurality of delayed differential input signals each having a delay greater than the next;

a first resistor and a second resistor having first terminals coupled to the second end of the serial string of differential delay lines and second terminals coupled to a second voltage level; and

a plurality of sampler circuits coupled to the serial string of differential delay lines at one end and a plurality of output terminal pairs of a plurality of outputs at another end, the plurality of sampler circuitry to receive a control signal and a third voltage level.

18. The multiple sampler circuit of claim 17 wherein,

each of the plurality of sampler circuits including

a first differentially-paired-transistors (DPT) having a pair of control terminals coupled to the control signal, a pair of source terminals coupled to a respective delayed differential input signal, a pair of drain terminals coupled to a pair of source terminals of a second DPT;

the second DPT having a pair of control terminals coupled to the third voltage level, a pair of drain terminals coupled to a pair of output terminals of a respective output, the pair of source terminals coupled to the pair of drain terminals of the first DPT; and

a third DPT having a pair of control terminals coupled to the control signal, a pair of drain terminals coupled to a high level power supply, a pair of source terminals coupled to the pair of source terminals of the second DPT and the pair of drain terminals of the first DPT.

19. The multiple sampler circuit of claim 17 wherein,

the plurality of sampler circuits sample the respective delayed differential input signals when the control signal slews to a voltage level to turn on the first DPT in each respective sampler circuit of the plurality of sampler circuits.

20. The multiple sampler circuit of claim 17 wherein,

each output terminal of the plurality of output terminal pairs of the plurality of outputs having one end of a resistor and a capacitor coupled thereto with an opposite end of the resistor and the capacitor coupled to the high level power supply.

21. The multiple sampler circuit of claim 17 further comprising:

the current source coupled to the differential transistor pair at a first end and a low level power supply at a second end opposite the first end.

22. The multiple sampler circuit of claim 17 further comprising:

a fourth differentially-paired-transistors (DPT) coupled between the differential transistor pair and the serial string of differential delay lines, the fourth DPT having a pair of control terminals coupled to a first voltage level, a pair of drain terminals coupled to the serial string of differential delay lines at a first end, a pair of source terminals coupled to the pair of drain terminals of differential transistor pair at a second end.

23. The multiple sampler circuit of claim 18 wherein,

transistors of the differential transistor pair and the plurality of sampler circuits are transistors of one of Gallium Arsenide (GaAs) MESFET, GaAs Heterojunction Bipolar Transistor (HBT), GaAs High Electron Mobility Transistor (HEMT), Indium Phosphide (InP) transistor, Silicon-Germanium (SiGe), Silicon bipolar or MOS transistors.

24. A parallel multiple sampler circuit comprising:

a first sampler circuit coupled to one or more input terminals to receive an input signal and one or more output terminals of a first output to generate a first output signal thereon, the first sampler circuit to receive a sample control signal, a first voltage level, and a second voltage level, the first sampler circuit including level activated switching elements responsive to the sample control signal and the first and second voltage levels to couple a first sample of the input signal to the first output as the first output signal;

a second sampler circuit coupled in parallel with the first sampler circuit to the one or more input terminals to receive the input signal, the second sampler circuit further coupled to one or more output terminals of a second output to generate a second output signal thereon, the second sampler circuit to receive the sample control signal, a third voltage level, and a fourth voltage level, the second sampler circuit including level activated switching elements responsive to the sample control signal and the first and second voltage levels to couple a second sample of the input signal to the second output as the second output signal; and

wherein the sample control signal to slew over a voltage range to sequentially trigger sampling of the input signal by the first and second sampler circuits.

25. The parallel multiple sampler circuit of claim 24 wherein,

the first sampler circuit to sample the input signal when a voltage of the sample control signal is between the first voltage level and the second voltage level.

26. The parallel multiple sampler circuit of claim 25 wherein,

the second sampler circuit to sample the input signal when the voltage of the sample control signal is between the third voltage level and the fourth voltage level.

27. The parallel multiple sampler circuit of claim 25 wherein,

the second voltage level is equal to the third voltage level, and

the second sampler circuit to sample the input signal when the voltage of the sample control signal is between the second voltage level and the fourth voltage level.

28. The parallel multiple sampler circuit of claim 24 further comprising:

N sampler circuits coupled in parallel with the first sampler circuit and the second sampler circuit to the one or more input terminals to receive the input signal, the N sampler circuits further coupled to one or more output terminals of N outputs to generate N output signals thereon, each of the N sampler circuits to receive the sample control signal, an (N+5)^th voltage level, and an (N+6)^th voltage level, the N sampler circuits including level activated switching elements responsive to the sample control signal and the (N+5)^th and (N+6)^th voltage levels to couple an N^th sample of the input signal to the N^th output as the N^th output signal; and

wherein the sample control signal to slew over a voltage range to sequentially trigger sampling of the input signal by the first, second, and N sampler circuits.

29. The parallel multiple sampler circuit of claim 24 wherein,

the level switching elements are differentially paired transistors.

30. The parallel multiple sampler circuit of claim 29 wherein,

the transistors are one of Gallium Arsenide (GaAs) MESFET, GaAs Heterojunction Bipolar Transistor (HBT), GaAs High Electron Mobility Transistor (HEMT), Indium Phosphide (InP) transistor, Silicon-Germanium (SiGe), Silicon bipolar or MOS transistors.

31. A multiple data sampling method comprising:

delaying an input data signal along a series of delay lines to generate a delayed sequence of input data signals;

providing a control signal changing from a first voltage level to a second voltage level;

simultaneously sampling the delayed sequence of input data signals in response to a change in the voltage level of the control signal between the first voltage level and the second voltage level; and

maintaining the samples of the delayed sequence of input data signals in response to the voltage level of the control signal being outside a range of voltage levels between the first voltage level and the second voltage level.

32. The method of claim 31 wherein,

the sampling of the data input signal initiates at a first switching point and ends at a second switching point between the range of voltage levels between the first voltage level and the second voltage level forming a sampling window.

33. A multiple data pulsing method comprising:

providing a control signal changing from a first voltage level to a second voltage level;

generating a series of a plurality of pulses in an output signal in response to a change in the voltage level of the control signal between the first voltage level and the second voltage level; and

maintaining a steady state in the output signal in response to the voltage level of the control signal being outside a range of voltage levels between the first voltage level and the second voltage level.

34. The method of claim 33 wherein,

the generating of a first pulse of the series of the plurality of pulses in the output signal initiates at a first switching point and ends at a second switching point between the range of voltage levels between the first voltage level and the second voltage level.

35. The method of claim 33 wherein,

the series of the plurality of pulses is non-overlapping.

36. The method of claim 33 wherein,

the series of the plurality of pulses is partially overlapping.

37. A multiple data sampling method comprising:

providing a control signal changing from a first voltage level to a second voltage level;

generating a series of a plurality of sampling apertures in a sampling circuit in response to a change in the voltage level of the control signal between the first voltage level and the second voltage level;

sequentially sampling an input signal in response to the series of the plurality of sampling apertures; and

generating a plurality of output signals in response to the sequential sampling of the input signal.

38. The method of claim 37 wherein,

the generating of a first sampling aperture initiates at a first switching point and ends at a second switching point between the range of voltage levels between the first voltage level and the second voltage level.

39. The method of claim 37 wherein,

the series of the plurality of sampling apertures is non-overlapping.

40. The method of claim 37 wherein,

the series of the plurality of sampling apertures is partially overlapping.

41. A multiple data sampling method in a circuit without differentiating circuit elements and without pulse reversing elements, the method comprising:

providing an electrical control signal;

generating a series of a plurality of sampling apertures in a sampling circuit, each sampling aperture having a starting time and an ending time, the series of the plurality of sampling apertures generated in response to a single transition of the electrical control signal.

42. The multiple data sampling method of claim 41 wherein,

the differentiating circuit elements are capacitors.

43. The multiple data sampling method of claim 41 wherein,

the pulse reversing elements are transmission lines.

44. The multiple data sampling method of claim 41 wherein,

the pulse reversing elements are delay lines.

45. A multiple pulse generating method in a circuit without differentiating circuit elements and without pulse reversing elements, the method comprising:

providing an electrical control signal;

generating a series of a plurality of output signals, each of the plurality of output signals having two transitions, and the series of the plurality of output signals generated in response to a single transition of the electrical control signal.

46. The multiple pulse generating method of claim 45 wherein,

the differentiating circuit elements are capacitors.

47. The multiple pulse generating method of claim 45 wherein,

the pulse reversing elements are transmission lines.

48. The multiple pulse generating method of claim 45 wherein,

the pulse reversing elements are delay lines.

49. A serial multiple sampler circuit for taking N samples where N is greater than or equal to four, the serial multiple sampler circuit comprising:

at least N−

1 reference voltage inputs to receive N−

1 reference voltage levels;

a differential transistor pair having control terminals coupled to input terminals to receive a differential data input signal for sampling, the differential transistor pair jointly coupled to a current source at one end and forming a centerline of the serial multiple sampler circuit;

a first left sampler circuit to the left of the centerline coupled between the differential transistor pair and a first left output, the first left sampler circuit to receive at least one of the N−

1 reference voltage levels and a sample control signal, the first sampler circuit including level activated switching elements responsive to the sample control signal and the at least one of the N−

1 reference voltage levels to couple a sample of the differential data input signal to the first left output;

a first right sampler circuit to the right of the centerline coupled between the differential transistor pair and a first right output, the first right sampler circuit to receive at least one of the N−

1 reference voltage levels and a first shifted sample control signal, the first right sampler circuit including level activated switching elements responsive to the first shifted sample control signal and the at least one of the N−

1 reference voltage levels to couple a sample of the differential data input signal to the first right output, the first shifted sample control signal having a first level shift from the sample control signal;

an i^th left sampler circuit to the left of the centerline coupled to the i−

1 left sampler circuit and an i^th left output, the i^th left sampler circuit between the i^th left output and the differential transistor pair, the i^th left sampler circuit to receive at least one of the N−

1 reference voltage levels and the sample control signal, the i^th left sampler circuit including level activated switching elements responsive to the sample control signal and the at least one of the N−

1 reference voltage levels to couple a sample of the differential data input signal to the i^th left output;

a j^th right sampler circuit to the right of the centerline coupled to the j−

1 right sampler circuit and a j^th right output, the j^th right sampler circuit between the j^th right output and the differential transistor pair, the j^th right sampler circuit to receive at least one of the N−

1 reference voltage levels and a j^th shifted sample control signal, the j^th right sampler circuit including level activated switching elements responsive to the j^th shifted sample control signal and the at least one of the N−

1 reference voltage levels to couple a sample of the differential data input signal to the j^th right output, the j^th shifted sample control signal having a j^th level shift from the sample control signal;

and

wherein the samples of the differential data input signal to be generated in response to a single transition of the sample control signal.

50. The serial multiple sampler circuit of claim 49 wherein,

N equals four, i equals two, j equals two,

the i^th left sampler circuit is the second left sampler circuit, and

the j^th right sampler circuit is the second right sampler circuit.

51. The serial multiple sampler circuit of claim 49 wherein,

N is an even number,

i is equal to j, and

i and j take on all consecutive integer values from two through N/2.

52. The serial multiple sampler circuit of claim 51 wherein,

the i^th left sampler circuit is one or more left sampler circuits, and

the j^th right sampler circuit is one or more right sampler circuits.

53. The serial multiple sampler circuit of claim 49 wherein,

N is an odd number,

i takes on all consecutive integer values from two through (N+1)/2, and

j takes on all consecutive integer values from two through N/2.

54. The serial multiple sampler circuit of claim 53 wherein,

the i^th left sampler circuit is one or more left sampler circuits, and

the j^th right sampler circuit is one or more right sampler circuits.

55. The serial multiple sampler circuit of claim 49 wherein,

N is an odd number,

i takes on all consecutive integer values from two through N/2, and

j takes on all consecutive integer values from two through (N+1)/2.

56. The serial multiple sampler circuit of claim 55 wherein,

the i^th left sampler circuit is one or more left sampler circuits, and

the j^th right sampler circuit is one or more right sampler circuits.