Manufacturing method of a semiconductor device having a polysilicon electrode

• US 20030049909A1
• Filed: 03/08/2002
• Published: 03/13/2003
• Est. Priority Date: 09/13/2001
• Status: Active Grant

• Current Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: Kim, Jong-Hwan, Lee, Suk-Kyun, Choi, Yongcheol, Kim, Cheol-Joong
• Granted Patent: US 6,740,562 B2
• Time in Patent Office: Days
• US Class Current: 438/309
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/8224 comprising a combination of vertical and lateral transistors
• CPC Class Codes: H01L 27/0658 Vertical bipolar transistor in combination with resistors or capacitors
• CPC Class Codes: H01L 27/067 Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
• CPC Class Codes: H01L 29/6625 Lateral transistors H01L29/66242 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence

Abstract

A semiconductor device and a method of manufacturing the semiconductor device having a vertical NPN bipolar transistor, a lateral PNP bipolar transistor, and P-type and N-type resistors are disclosed. In one embodiment, a photoresist pattern is formed on a pad oxide layer and field oxides on an N-type epitaxial layer that is grown on a P-type semiconductor substrate. The pad oxide layer is etched after implanting P-type impurity into the epitaxial layer by using the photoresist pattern as a mask. Deposition of a polysilicon layer after removing the photoresist pattern is followed by implanting P-type impurity and N-type impurity into the polysilicon layer in sequence. Another photoresist pattern formed on the polysilicon layer after the previous implantation is used as an etch mask for etching the polysilicon layer to form polysilicon electrodes of transistors and P-type and N-type resistors as well as expose the surface of the epitaxial layer near an emitter region of the vertical transistor. P-type impurity is implanted into the epitaxial layer through the exposed surface thereof by using the photoresist pattern as an implant mask. The structure is then subjected to heat treatment to form emitter, intrinsic and extrinsic base, and collector regions of the transistors.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming a collector region of a first conductivity type in a semiconductor body of the first conductivity type;

depositing a polysilicon layer on the semiconductor body;

introducing a first dose of a first impurity of a second conductivity type into the polysilicon layer;

introducing a second dose of a second impurity of the first conductivity type into the polysilicon layer, the second dose being greater than the first dose;

patterning the polysilicon layer to form a collector poly electrically connected to the collector region and an emitter poly spaced apart from the collector poly; and

heat treating the semiconductor body having the collector poly and the emitter poly thereon to form an emitter region of the first conductivity type adjacent the emitter poly and a base region of the second conductivity type adjacent the emitter region.

2. The method of claim 1, further comprising introducing a third impurity of the second conductivity type into the semiconductor body after forming the emitter poly and before the heat treatment, thereby forming an extrinsic base region after the heat treatment.

3. The method of claim 1, wherein the patterning further comprises:

forming a photoresist pattern on the polysilicon layer;

etching the polysilicon layer using the photoresist pattern as an etch mask;

introducing a third impurity of the second conductivity type into the semiconductor body by using the photoresist pattern as a mask, thereby forming an extrinsic base region after the heat treatment.

4. The method of claim 1, wherein diffusion rate of the first impurity is larger than diffusion rate of the second impurity.

5. The method of claim 1, wherein the semiconductor body comprises an epitaxial layer and a buried layer of the first conductivity type connected to the collector region.

6. The method of claim 1, further comprising introducing a third impurity of the second conductivity type into the semiconductor body before depositing the polysilicon layer.

7. The method of claim 1, further comprising:

forming a pad layer on the semiconductor body before forming the collector region; and

forming a first contact hole through the pad layer exposing at least a portion of the collector region and forming a second contact hole through the pad layer exposing at least a portion of the epitaxial layer before depositing the polysilicon layer, thereby causing the polysilicon layer to contact the epitaxial layer through the first and the second contact holes.

8. The method of claim 7, further comprising introducing a third impurity of the second conductivity type into the semiconductor body before depositing the polysilicon layer.

9. The method of claim 1, further comprising:

forming a pad layer on the semiconductor body before forming the collector region; and

removing the pad layer before depositing the polysilicon layer.

10. The method of claim 9, further comprising introducing a third impurity of the second conductivity type into the semiconductor body before depositing the polysilicon layer.

11. The method of claim 1, wherein the second dose is 1.0-5.0×

10¹⁴ atoms/cm² and the first dose is 9.0×

10¹⁵-1.0×

10¹⁶ atoms/cm².

12. The method of claim 1, wherein the polysilicon layer has a first portion which is not subject to the introduction of the second impurity, and the first portion of the polysilicon layer is separated from both the emitter poly and the collector poly to become a resistor of the second conductivity type after the patterning of the polysilicon layer.

13. A method for manufacturing a semiconductor device comprising:

forming a collector region of a first conductivity type in a semiconductor body of the first conductivity type;

depositing a polysilicon layer on the semiconductor body;

forming a photoresist pattern on the polysilicon layer;

etching the polysilicon layer to form an emitter poly by using the photoresist pattern as an etch mask;

introducing first impurity of a second conductivity type for an extrinsic base region into the semiconductor body by using the photoresist pattern a mask;

removing the photoresist pattern; and

forming an emitter region of the first conductivity type, an intrinsic base region of the second conductivity type under the emitter region, the extrinsic base region being connected to the intrinsic base region.

14. The method of claim 13, further comprising:

introducing a second impurity of the second conductivity type into at least a first portion of the polysilicon layer before forming the photoresist pattern; and

introducing a third impurity of the first conductivity type into the polysilicon layer except for at least the first portion of the polysilicon layer before forming the photoresist pattern, wherein the etching further forms a resistor of the first portion of the polysilicon layer separated from the emitter poly.

15. A method for manufacturing a semiconductor device comprising:

forming a collector region of first conductivity type in a semiconductor body of the first conductivity type;

depositing a polysilicon layer on the semiconductor body;

introducing an impurity of second conductivity type into the polysilicon layer without using photolithography;

forming a photoresist pattern covering at least one portion of the polysilicon layer;

introducing impurity of the first conductivity type into the polysilicon layer by using the photoresist pattern as a mask;

removing the photoresist pattern; and

patterning the polysilicon layer to form a collector poly and an emitter poly of the first conductivity type and a resistor of the second conductivity type which are spaced apart from one another.

16. A method of manufacturing a semiconductor device comprising:

forming a first sink region in a vertical region of a semiconductor body having an insulating layer thereon and a second sink region in a lateral region of the semiconductor body;

forming a first photoresist pattern on the insulating layer, the first photoresist pattern having openings exposing portions of the insulating layer;

etching the insulating layer by using the first photoresist pattern;

depositing a polysilicon layer;

introducing an impurity of a second conductivity type with a first dose into the polysilicon layer without any lithography mask;

forming a second photoresist pattern covering a portion of the polysilicon layer;

introducing impurity of a first conductivity type with a second dose higher than the first dose into the polysilicon layer using the second photoresist pattern as a mask;

forming a third photoresist pattern after removing the second photoresist pattern;

etching the polysilicon layer by using the third photoresist pattern as an etch mask to form first, second, and emitter polys and a first resistor of the first conductivity type and a second resistor of the second conductivity type, the first and the second polys contacting the first and the second sink regions, respectively;

introducing impurity of the second conductivity type into the semiconductor body using the third photoresist pattern a mask; and

heat treating the semiconductor body to form an emitter region of the first conductivity type, an intrinsic base region of the second conductivity type, and an extrinsic base region of the second conductivity type.

17. The method of claim 16, further comprising introducing impurity of the second conductivity type for the intrinsic base region into the semiconductor body using the first photoresist pattern as a mask.