Low temperature gate stack

• US 20030049942A1
• Filed: 08/22/2002
• Published: 03/13/2003
• Est. Priority Date: 08/31/2001
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Tuominen, Marko, Shero, Eric, Haukka, Suvi, Pomarede, Christophe, Hub Maes, Jan Willem
• Granted Patent: US 6,806,145 B2
• Time in Patent Office: Days
• US Class Current: 438/778
• CPC Class Codes: H01L 21/02052 Wet cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

The present invention relates to methods for forming dielectric layers on a substrate, such as in an integrated circuit. In one aspect of the invention, a thin interfacial layer is formed. The interfacial layer is preferably an oxide layer and a high-k material is preferably deposited on the interfacial layer by a process that does not cause substantial further growth of the interfacial layer. For example, water vapor may be used as an oxidant source during high-k deposition at less than or equal to about 300° C.

Claims

1. A process for forming a gate dielectric on a semiconductor substrate, the method comprising:

forming an interfacial dielectric oxide layer on the substrate; and

depositing a high-k layer over the interfacial dielectric layer under conditions such that the thickness of the interfacial dielectric layer is not substantially increased while depositing the high-k layer.

2. The process of claim 1, wherein the temperature at which the high-k layer is deposited is less than or equal to 300°

C.

3. The process of claim 2, wherein depositing comprises providing H₂O to the substrate as an oxygen source.

4. The process of claim 1, wherein the thickness of the interfacial layer is less than about 15 Å

.

5. The process of claim 4, wherein the thickness of the interfacial layer is less than about 10 Å

.

6. The process of claim 5, wherein the thickness of the interfacial layer is less than about 5 Å

.

7. The process of claim 1, wherein said interfacial dielectric oxide layer is SiO₂.

8. The process of claim 7, wherein the interfacial dielectric layer is formed by thermal oxidation of the substrate.

9. The method of claim 8, wherein thermal oxidation comprises oxidation through an oxidation-moderating surface termination.

10. The process of claim 1, wherein depositing comprises an atomic layer deposition (ALD) process.

11. The process of claim 10, wherein the ALD process comprises a plurality of cycles, each cycle comprising:

contacting a substrate in a reaction chamber with a first reactant;

removing the unreacted first reactant from the reaction chamber;

contacting the substrate with a second reactant; and

removing the unreacted second reactant from the reaction chamber.

12. The process of claim 11, wherein said second reactant is water vapor.

13. The process of claim 12, wherein the ALD process is carried out at less than 300°

C.

14. The process of claim 13, wherein the high-k layer comprises Al₂O₃.

15. The method of claim 14, wherein the first reactant is trimethyl aluminum (TMA) and the second reactant is H₂O.

16. The method of claim 13, wherein the high-k layer comprises ZrO₂.

17. The method of claim 16, wherein the first reactant is ZrCl₄ and the second reactant is H₂O.

18. A process for forming a compound dielectric layer on the surface of a substrate comprising forming an oxide layer less than about 15 Å

thick and depositing a high-k material on top of the oxide layer without growing the oxide layer further.

19. The process of claim 18, wherein the oxide layer is less than about 10 Å

thick.

20. The process of claim 19, wherein the oxide layer is less than about 5 Å

thick.

21. The process of claim 18, further comprising cleaning the substrate prior to forming the oxide layer.

22. The process of claim 18, wherein the substrate is silicon.

23. The process of claim 22, wherein the oxide layer is formed by thermal oxidation of the silicon substrate.

24. The process of claim 18, wherein the high-k material is deposited by an ALD type process comprising sequential surface reactions wherein the substrate is sequentially and alternatingly exposed to a first metal containing compound and a second oxidizing compound.

25. The process of claim 24, wherein the second oxidizing compound is a metal organic compound.

26. The process of claim 24, wherein the first metal containing compound is a metal halide and the second oxidizing compound is a metal alkoxide.

27. The process of claim 24, wherein the first metal containing compound and the second oxidizing compound are both metal alkoxides.

28. The process of claim 24, wherein the metal containing compound is selected from the group consisting of ZrO₂, HfO₂, Ta₂O₅, TiO₂, BST, ST, SBT, Al₂O₃, Nb₂O₅ and La₂O₃.

29. The process of claim 24, wherein the oxidizing compound is water vapor.

30. The process of claim 24, wherein the temperature is less than 300°

C.

31. The process of claim 18, wherein the high-k material is deposited by direct decomposition of a metal source compound.

32. The process of claim 18, wherein the high-k material is deposited by a process selected from the group consisting of CVD and MOCVD.

33. The process of claim 32, wherein the temperature is less than 300°

C.

34. The process of claim 32, wherein water vapor is used as an oxidizing agent.

35. The process of claim 18, wherein the oxide layer comprises SiO₂.

36. The process of claim 35, wherein the oxide layer additionally comprises nitrogen.

37. The process of claim 18, additionally comprising modifying any surface termination on the oxide layer prior to depositing the high-k material.

38. A method of forming a dielectric layer on a silicon substrate comprising:

growing a silicon oxide interface layer on the substrate, the interface layer having a thickness of less than about 15 Å

; and

depositing a high-k material on top of the interface layer,

wherein depositing comprises maintaining the substrate at a temperature less than about 300°

C. and supplying water vapor as an oxidizing agent.

39. The method of claim 38 wherein depositing comprises an ALD process.

40. The method of claim 39, wherein the ALD process comprises a plurality of cycles, each cycle comprising:

contacting the substrate with a first reactant;

removing the unreacted first reactant from the reaction chamber;

contacting the substrate with water vapor; and

removing the unreacted water vapor from the reaction chamber.

41. The method of claim 38, wherein the interface layer grows by less than about 15 Å

during deposition of the high-k material.

42. The method of claim 41, wherein the interface layer grows by less than about 10 Å

.

43. The method of claim 42, wherein the interface layer grows by less than about 5 Å

.