Memory device in mobile phone

• US 20030050087A1
• Filed: 12/13/2001
• Published: 03/13/2003
• Est. Priority Date: 09/07/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Taeyoun
• Granted Patent: US 7,496,377 B2
• Time in Patent Office: Days
• US Class Current: 455/550.1
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

A memory device for a mobile phone is provided. The memory device includes a flash memory for storing program data and user data; an interface circuit configured for interfacing the flash memory to a microprocessor; a first memory for copying the program data of the flash memory; and a second memory for executing the program data of the first memory wherein the first and second memories are independent memories. The flash memory is a NAND-type flash memory and the interface circuit is an application-specific integrated circuit (ASIC) including a read-only memory (ROM) for storing program codes and an error correction circuit. Additionally, the first and second memories are preferably random-access memories (RAM). By utilizing a NAND-type flash memory in place of a conventional NOR-type flash memory, the memory device can achieve a larger storage capacity at a lower cost.

Claims

1. A memory device for a mobile phone comprising:

a flash memory for storing program data and user data;

an interface circuit configured for interfacing the flash memory to a microprocessor;

a first memory for copying the program data of the flash memory; and

a second memory for executing the program data of the first memory wherein the first and second memories are independent memories.

2. A memory device as in claim 1, wherein the flash memory is a NAND-type flash memory.

3. A memory device as in claim 1, wherein the first and second memories are random-access memories (RAM).

4. A memory device as in claim 1, wherein the interface circuit is an application-specific integrated circuit (ASIC) including a read-only memory (ROM) for storing program codes and an error correction circuit.

5. A memory device as in claim 1, wherein the interface circuit comprises a first logic gate for generating a NAND CE (chip enable) signal, said NAND CE signal enabling the flash memory.

6. A memory device as in claim 5, wherein the interface circuit further comprises a second logic gate for generating a CLE (command latch enable) signal, said CLE signal informing the flash memory that incoming data is a command.

7. A memory device as in claim 6, wherein the interface circuit further comprises a third logic gate for generating a ALE (address latch enable) signal, said ALE signal informing the flash memory that incoming data is an address.

8. A memory device as in claim 5, wherein the first logic gate is an OR gate for receiving a CS (chip select) signal from the microprocessor and a CE (chip enable) signal from the microprocessor for generating said NAND CE signal.

9. A memory device as in claim 6, wherein the second logic gate is an AND gate for receiving a command signal from the microprocessor and a CS (chip select) signal from the microprocessor for generating said CLE signal.

10. A memory device as in claim 7, wherein the third logic gate is an AND gate for receiving an address signal from the microprocessor and a CS (chip select) signal from the microprocessor for generating said ALE signal.

11. A mobile communication device comprising:

an analog circuit for air interfacing the mobile communication device;

a user interface circuit for interfacing between the mobile communication device and a user;

a microprocessor (MPU) for providing overall control of the operation of the mobile device; and

a memory device including

a flash memory for storing program data and user data;

an interface circuit for interfacing the flash memory to the microprocessor;

a first memory for copying the program data of the flash memory; and

a second memory for executing the program data of the first memory wherein the first and second memories are independent memories.

12. A mobile communication device as in claim 11, wherein the flash memory is a NAND-type flash memory.

13. A mobile communication device as in claim 11, wherein the first and second memories are random-access memories (RAM).

14. A mobile communication device as in claim 11, wherein the interface circuit is an application-specific integrated circuit (ASIC) including a read-only memory (ROM) for storing program codes and an error correction circuit.

15. A mobile communication device as in claim 11, wherein the interface circuit comprises a first logic gate for generating a NAND CE (chip enable) signal, said NAND CE signal enabling the flash memory.

16. A mobile communication device as in claim 15, wherein the interface circuit further comprises a second logic gate for generating a CLE (command latch enable) signal, said CLE signal informing the flash memory that incoming data is a command.

17. A mobile communication device as in claim 16, wherein the interface circuit further comprises a third logic gate for generating a ALE (address latch enable) signal, said ALE signal informing the flash memory that incoming data is an address.

18. A mobile communication device as in claim 15, wherein the first logic gate is an OR gate for receiving a CS (chip select) signal from the microprocessor and a CE (chip enable) signal from the microprocessor for generating said NAND CE signal.

19. A mobile communication device as in claim 16, wherein the second logic gate is an AND gate for receiving a command signal from the microprocessor and a CS (chip select) signal from the microprocessor for generating said CLE signal.

20. A mobile communication device as in claim 17, wherein the third logic gate is an AND gate for receiving an address signal from the microprocessor and a CS (chip select) signal from the microprocessor for generating said ALE signal.