Semiconductor device and method for fabricating the same

• US 20030052374A1
• Filed: 09/12/2002
• Published: 03/20/2003
• Est. Priority Date: 09/14/2001
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Kee-Jeung, Oh, Jong-Hyuk
• Granted Patent: US 6,849,505 B2
• Time in Patent Office: Days
• US Class Current: 257/406
• CPC Class Codes: C23C 16/308 Oxynitrides
• CPC Class Codes: C23C 16/403 of aluminium, magnesium or beryllium
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02299 pre-treatment
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

Disclosed is a semiconductor device having a double dielectric layer, wherein the double dielectric layer comprises a first dielectric layer having aluminum and a second dielectric layer, of which a dielectric constant is higher than that of the first dielectric layer, stacked on the first dielectric layer. Also disclosed are methods for fabricating the semiconductor device.

Claims

1. A semiconductor device having a double dielectric layer, wherein the double dielectric layer comprises;

a first dielectric layer having aluminum; and

a second dielectric layer stacked on the first dielectric layer, said second dielectric layer having a dielectric constant higher than that of the first dielectric layer.

2. The semiconductor device as recited in claim 1, wherein the first dielectric layer is an Al₂O₃ layer.

3. The semiconductor device as recited in claim 1, wherein the second dielectric layer is formed with a layer selected from the group consisting of an oxide layer having tantalum, an oxide layer having a perovskite structure and a combination thereof.

4. The semiconductor device as recited in claim 3, wherein the oxide layer having tantalum is a TaON layer, a Ta₂O₅ layer or a BST layer.

5. A semiconductor device comprising:

a semiconductor substrate;

a first gate electrode on the semiconductor substrate;

a first gate insulating layer comprising aluminum on said first gate electrode;

a second gate insulating layer stacked on the first insulating layer, said second dielectric layer having a dielectric constant higher than that of the first gate insulating layer; and

a second gate electrode on the second gate insulating layer.

6. The semiconductor device as recited in claim 5, wherein the first gate insulating layer comprises an Al₂O₃ layer.

7. The semiconductor device as recited in claim 5, wherein the second gate insulating layer is formed of a layer selected from the group consisting of a TaON layer, a Ta₂O₅ layer and a BST layer.

8. The semiconductor device as recited in claim 5, wherein the first and second gate electrodes are formed with a silicon layer having at least a doped polysilicon layer or a doped amorphous silicon layer, a metal layer having at least TiN, TaN, W, WN, Ru, Ir or Pt or a silicide layer having at least CoSi, MoSi or WSi.

9. The semiconductor device as recited in claim 5, further comprising a nitride layer between the first gate electrode and the first gate insulating layer.

10. The semiconductor device as recited in claim 5, wherein the first gate insulating layer is formed at a thickness of 10 Å

to 20 Å

.

11. The semiconductor device as recited in claim 5, wherein the second gate insulating layer is formed at a thickness of 50 Å

to 100 Å

.

12. The semiconductor device as recited in claim 5, wherein the surface of the first gate electrode is uneven.

13. A method for fabricating a semiconductor device comprising the steps of:

a) providing a semiconductor substrate;

b) forming a first gate electrode on the semiconductor substrate;

c) forming a first gate insulating layer a semiconductor substrate having aluminum;

d) forming a second gate insulating layer on the first gate insulating layer, said second gate insulating layer having a dielectric constant higher than that of the first gate insulating layer; and

e) forming a second gate electrode on the second gate insulating layer.

14. The method as recited in claim 13, further comprising the steps of performing a thermal treatment process of the first and second gate insulating layers after forming the first and second gate insulating layers.

15. The method as recited in claim 14, wherein the thermal process is carried out by a rapid thermal process at a temperature of about 800°

C. to about 950°

C. or by an electro-furnace process at a temperature of about 700°

C. to about 800°

C.

16. The method as recited in claim 13, wherein the first gate insulating layer is formed by an Al₂O₃ layer.

17. The method as recited in claim 13, wherein the second gate insulating layer is formed by a layer selected from a group of a TaON layer, a Ta₂O₅ layer and a BST layer.

18. The method as recited in claim 13, further comprising a step of performing a surface treatment process to remove a native oxide layer on a surface of the first gate electrode after forming the first electrode.

19. The method as recited in claim 18, wherein the surface treatment process is carried out by using a HF gas or a HF solution.

20. The method as recited in claim 19, further comprising a step of performing a boundary treatment process by using a NH₄OH solution or a H₂SO₄ solution before or after the surface treatment process.

21. The method as recited in claim 13, further comprising a step of performing a nitride treatment process of a surface the first gate electrode to in-situ or ex-situ.

22. The method as recited in claim 21, wherein the nitride treatment process is carried out in an atmosphere-of a NH₃ gas or a N₂/H₂ gas and at a temperature of about 300°

C. to about 500°

C.

23. The method as recited in claim 21, wherein the nitride treatment process is carried out by a rapid thermal process at a temperature of about 750°

C. to about 950°

C. and in an atmosphere of a NH₃ gas for 30 seconds to 120 seconds.

24. The method as recited in claim 21, wherein the nitride treatment process is carried out by an electro-furnace process at a temperature of about 500°

C. to about 1000°

C. and in an atmosphere of a NH₃ gas.

25. The method as recited in claim 13, wherein the step c) is carried out by a low pressure chemical vapor deposition process or a atomic layer deposition process with an Al₂O₃ layer.

26. The method as recited in claim 25, wherein the low pressure chemical vapor deposition process of the Al₂O₃ layer is carried out by evaporation of an Al(OC₂H5)₃ solution adding oxygen, which a chemical vapor having aluminum is provided to an evaporator or an evaporating tube through a flow controller, at a temperature of about 150°

C. to about 300°

C.

27. The method as recited in claim 13, wherein the step d) is carried out by a low pressure chemical vapor deposition (LPCVD) process or an atomic layer deposition (ALD) process with a layer selected from the group consisting of a TaON layer, a Ta₂O₅ layer and a BST layer.

28. The method as recited in claim 27, wherein a Ta bearing vapor gas and a reaction gas, which is a NH₃ gas at a pressure of 10 sccm to 1000 sccm or a O₂ gas at a pressure of 0 sccm to 300 sccm, are injected through a mass flow controller (MFC) onto a wafer in the low pressure chemical vapor deposition chamber maintained at a temperature of about 300°

C. to about 600°

C. and at a pressure of 0.1 torr to 5 torr and then the TaON layer is formed by a surface chemical reaction.

29. The method as recited in claim 28, wherein The Ta bearing vapor gas is generated by evaporating an organic metal compound having Ta(OC₂H₅)₅ or Ta(N(CH₃)₂)₅ of over 99.999% at a temperature of about 150°

C. to about 200°

C. injected through a flow controller and, in order to prevent a condensation of the vapor gas, the Ta bearing vapor gas is injected to a LPCVD chamber maintained at a temperature of about 150°

C. to about 200°

C. and at a pressure of 0.1 torr to 5 torr.