Semiconductor device

• US 20030052400A1
• Filed: 08/05/2002
• Published: 03/20/2003
• Est. Priority Date: 08/09/2001
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Okura, Yasushi, Mamitsu, Kuniaki, Hirano, Naohiko
• Granted Patent: US 6,803,667 B2
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/33 of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device comprises a semiconductor element, a heat sink soldered to one surface of the semiconductor element, and a heat sink soldered to an opposite surface of the semiconductor element. The semiconductor element is provided with a wiring layer. The wiring layer is covered with an insulating protective film. The protective film is an organic film. The thickness of the wiring layer and that of the protective film are assumed to be t1 and t2, respectively. The wiring layer and the protective film are formed so as to establish a relationship of t1<t2. An elastic modulus of the protective film at room temperature is adjusted to 1.0-5.0 GPa and a thermal expansion coefficient of the protective film is adjusted to 35-65×10⁻⁶/°C. Even under a thermal stress the semiconductor device can diminish a short-circuit defect of the wiring layer.

Claims

1. A semiconductor device comprising:

a semiconductor element;

a first electrode layer formed on one main surface side of the semiconductor element;

an organic insulating protective film which covers the first electrode layer so as to straddle one region of the first electrode layer; and

an electrically conductive bonding material which overlaps an upper surface of the one region of the first electrode layer through the protective film,

wherein if the thickness up to the surface of the first electrode layer with respect to a peripheral portion of the first electrode layer is assumed to be t1 and a substantial thickness up to the surface of the protective film with respect to the peripheral portion of the first electrode layer is assumed to be t2, there exists the following relationship;

t1<

t2

12. A semiconductor device according to claim 1, wherein the protective film is constructed so as to have an elastic modulus at room temperature of 1.0-5.0 GPa and a thermal expansion coefficient of 35-65×

10<sup>−

6</sup>/°

C.

13. A semiconductor device according to claim 1, wherein the protective film is constructed so as to have an elastic modulus smaller than that of the bonding material and have a thermal expansion coefficient almost equal to that of the bonding material.

14. A semiconductor device according to claim 1, wherein the bonding material is solder.

20. A semiconductor device according to claim 1, wherein the protective film is a polyimide film.

2. A semiconductor device comprising:

a semiconductor element;

a first electrode layer formed on one main surface side of the semiconductor element;

a second electrode layer formed on the one main surface side of the semiconductor element to be spaced from the first electrode layer;

an electrically conductive bonding material having a region in contact with the second electrode layer and also having a region overlapping the first electrode layer;

an organic protective film, the protective film being disposed between the first electrode layer and the bonding material so as to cover the first electrode layer in the region where the first electrode layer and the bonding material overlap each other, thereby preventing contact of the first electrode layer with the bonding material; and

first metal blocks bonded electrically to the second electrode layer through the bonding material;

wherein if the thickness of the first electrode layer at a peripheral edge portion of the first electrode layer is assumed to be t1 and a substantial thickness of the protective film around the first electrode layer is assumed to be t2, there exists the following relationship;

t1<

t2

3. A semiconductor device according to claim 2, wherein the bonding material is an Sn-based solder, and given that a thermal expansion coefficient of the first metal block is α

1, that of the semiconductor element is α

2, a chip size of the semiconductor element is a×

b, and a temperature difference between highest and lowest temperatures in a working environment is Δ

T, there exists the following relationship;

4. A semiconductor device according to claim 2, further comprising a second metal block which is bonded to another main surface side of the semiconductor element through a bonding material.

5. A semiconductor device according to claim 4, wherein the bonding material is an Sn-based solder, and given that an apparent thermal expansion coefficient of a composite system comprising the first metal blocks disposed on the one main surface side of the semiconductor element and the Sn-based solder is α

1e, an apparent thermal expansion coefficient of a composite system comprising the second metal block disposed on the another main surface side of the semiconductor element and the semiconductor element is α

2e, a chip size of the semiconductor element is a×

b, and a temperature difference between highest and lowest temperatures in a working environment is Δ

T, there exists the following relationship;

6. A semiconductor device according to claim 3, further comprising a second metal block which is bonded to another main surface side of the semiconductor element through a bonding material.

7. A semiconductor device according to claim 6, wherein the bonding material is an Sn-based solder, and given that an apparent thermal expansion coefficient of a composite system comprising the first metal blocks disposed on the one main surface side of the semiconductor element and the Sn-based solder is α

1e, an apparent thermal expansion coefficient of a composite system comprising the second metal block disposed on the another main surface side of the semiconductor element and the semiconductor element is α

2e, a chip size of the semiconductor element is a×

b, and a temperature difference between highest and lowest temperatures in a working environment is Δ

T, there exists the following relationship;

8. A semiconductor device according to claim 4, wherein the semiconductor element is a vertical power semiconductor element, the first metal block constitutes a first terminal of the power semiconductor element, the second metal block constitutes a second terminal of the power semiconductor element, and the first electrode layer constitutes a control wiring of the power semiconductor element.

9. A semiconductor device according to claim 6, wherein the semiconductor element is a vertical power semiconductor element, the first metal block constitutes a first terminal of the power semiconductor element, the second metal block constitutes a second terminal of the power semiconductor element, and the first electrode layer constitutes a control wiring of the power semiconductor element.

10. A semiconductor device according to claim 4, wherein the semiconductor element, the first metal blocks and the second metal block are integrally sealed with resin.

11. A semiconductor device according to claim 6, wherein the semiconductor element, the first metal blocks and the second metal block are integrally sealed with resin.

15. A semiconductor device according to claim 2, wherein the protective film is constructed so as to have an elastic modulus at room temperature of 1.0-5.0 GPa and a thermal expansion coefficient of 35-65×

10<sup>−

6</sup>/°

C.

16. A semiconductor device according to claim 2, wherein the protective film is constructed so as to have an elastic modulus smaller than that of the bonding material and have a thermal expansion coefficient almost equal to that of the bonding material.

17. A semiconductor device comprising:

a semiconductor element;

heat sinks soldered to both surfaces of the semiconductor element;

a wiring layer formed on a surface of the semiconductor element; and

an organic protective film formed so as to cover the wiring layer,

wherein if the thickness of the wiring layer and that of the protective film are assumed to be t1 and t2, respectively, there exists a relationship of t1<

t2, and

the protective film is constructed so as to have an elastic modulus at room temperature of 1.0-5.0 GPa and a thermal expansion coefficient of 35-65×

10<sup>−

6</sup>/°

C.

18. A semiconductor device according to claim 17, wherein the soldering is performed using an Sn-based solder, and given that a thermal expansion coefficient of the heat sinks located on the surface side of the semiconductor element is α

1, a thermal expansion coefficient of the semiconductor element is α

2, a chip size of the semiconductor element is a×

b, and a temperature difference between highest and lowest temperatures in a working environment is Δ

T, there exists the following relationship;

19. A semiconductor device according to claim 17, wherein the soldering is performed using an Sn-based solder, and given that an apparent thermal expansion coefficient of a composite system comprising the heat sinks located on the surface side of the semiconductor element and the solder is α

1e, an apparent thermal expansion coefficient of a composite system comprising the heat sink located on a back side of the semiconductor element and the semiconductor element is α

2e, a chip size of the semiconductor element is a×

b, and a temperature difference between highest and lowest temperatures in a working environment is Δ

T, there exists the following relationship;

21. A semiconductor device comprising:

a semiconductor element;

a first electrode layer formed on one main surface side of the semiconductor element;

a second electrode layer formed on the one main surface side of the semiconductor element to be spaced from the first electrode layer;

an insulating protective film which covers the first electrode layer;

an electrically conductive bonding material having a region in contact with the second electrode layer and also having a region overlapping the first electrode layer; and

a first metal block bonded electrically to the second electrode layer through the bonding material,

wherein a surface asperity of a ground for the bonding material in the region overlapping the first electrode layer is flat or is concave above the first electrode layer.

22. A semiconductor device according to claim 21, wherein the first electrode layer is formed in a flat or concave shape with respect to a surface of a vicinity of the first electrode layer.

23. A semiconductor device according to claim 21, wherein the second electrode layer is disposed below the region of the bonding material overlapping the first electrode layer and above the first electrode layer through the protective film, and a surface of the second electrode layer constitutes the ground for the bonding material.

24. A semiconductor device according to claim 21, wherein the protective film has an organic protective film formed on a surface of the first electrode layer.